IBIS - EIA IBIS Open Forum Activity: RE: [IBIS] Miller Capacitan

From: Muranyi, Arpad <Arpad_Muranyi@mentor.com>
Date: Mon Jul 09 2012 - 07:11:40 PDT

Forgot to mention, that if you want to model the
feedback, you may do so with the [External Model]
keyword using the available languages (VHDL-AMS,
Verilog-A). But you will have to come up with the
model algorithm yourself then.

Arpad
===================================================

-----Original Message-----
From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Muranyi, Arpad
Sent: Monday, July 09, 2012 9:04 AM
To: ibis@eda.org
Subject: RE: [IBIS] Miller Capacitance

Amit,

That effect is basically a negative feedback. IBIS
models cannot model any kind of feedback, but the
[Ramp] or V-t table data do include its effects in
a static way.

In other words, the edge rate of the IBIS model is
correct at the conditions at which they were measured
in the lab or from the transistor level model. But
if the IBIS model's loading conditions are different
and the edge rate is consequently different, the
model will become less accurate.

These inaccuracies are usually negligible, but there
might be cases when they may be too large. For those
cases I would suggest that you try to measure the device
in the lab or from a transistor level model under the
new conditions and make another IBIS model for those
conditions.

I hope this helps.

Arpad
=========================================================

-----Original Message-----
From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Amit KUMAR STE
Sent: Monday, July 09, 2012 4:24 AM
To: Muranyi, Arpad; ibis@eda.org
Subject: RE: [IBIS] Miller Capacitance

Hello Arpad,

Yes am referring to the same case where output waveform modifies the gate voltage through miller capacitance.
Do you have any solution for such cases?

Lynne,

Can you elaborate a bit more on your method.
I dint get it :-(

Regards
Amit

-----Original Message-----
From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Muranyi, Arpad
Sent: Friday, July 06, 2012 11:26 PM
To: ibis@eda.org
Subject: RE: [IBIS] Miller Capacitance

Lynne,

You might be referring to slide 7 in this presentation:

http://www.eda.org/ibis/summits/jun03b/muranyi1.pdf

which gives an illustration on how the waveform on the gate of the output transistor changes due to Miller capacitance. But this presentation actually states that this feedback is assumed to be negligible in the IBIS behavioral buffer models and it is ignored in the model algorithm shown in this presentation.

Amit,

What Miller capacitance are you referring to? Are you talking about the same one the above presentation mentions?

Thanks,

Arpad
============================================================

-----Original Message-----
From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Lynne D. Green
Sent: Friday, July 06, 2012 12:21 PM
To: Amit KUMAR STE
Cc: ibis@eda.org
Subject: Re: [IBIS] Miller Capacitance

Hello, Amit,

As I remember, Arpad Muranyi has done at least one Summit presentation on this. Topics generally include input effects on output waveforms, input edge-rate sensitivity.

The way I have handled this: capture
transistor-level circuit containing 2-3 preceding stages on chip plus the selected I/O buffer. Use this in simulations for generating the IBIS waveform tables.

Hope this helps.

Lynne

"IBIS training when you need it, where you need it."

Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@mindspring.com

On 7/6/2012 2:18 AM, Amit KUMAR STE wrote:
> Hello Experts,
>
> Is there any way of taking miller capacitance into picture while doing ibis model of a simple single ended buffer?
> Please suggest me any presentation/document which I can refer for the same.
>
> Regards
> Amit
>

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