[IBIS] RE: Validation of IBIS 5.0 model with package parasitics

Hi Rinsha,

I've run across this same issue recently with an IBIS 5.0 power aware model I created.  I believe the problem is related to not having [Composite Current] waveforms for the ground currents.  The DDR4 memory device I modeled includes two supplies (VDD (core) and VDDQ (IO)) and two grounds (VSS (core) and VSSQ (IO)).  EDA software might assume that pre-driver currents for VCCQ are balanced for VSSQ, but this is not totally valid.  When significant parasitics are added to VSSQ, the correlation gets bad.  What I've found helps me is that VSS and VSSQ are shorted on the die.  The result is that the package impedance for VSSQ becomes quite small since it is now in parallel with VSS (which typically has low inductance in the package).  With a small package impedance on VSSQ/VSS, the correlation is pretty good to Spice.

It may be worth starting a conversation about whether [Composite Current] needs to be expanded to include modeling of ground currents.

Regards,
Randy

Randy Wolff
Micron Technology

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Rinsha Reghunath
Sent: Thursday, April 04, 2013 5:39 AM
To: ibis@eda.org; ibis-users@eda.org
Subject: [IBIS-Users] Validation of IBIS 5.0 model with package parasitics

Hi all,

I am trying to validate an IBIS 5.0 model at 500Mbps with package parasitics (R, L, C for supply, ground and pad) and on-die RC decoupling. The issue is that the I-T waveforms are not matching when I add inductance to the ground terminal. When I remove the inductance on the ground terminal keeping the rest of the setup same, the I-T waveforms correlate. Has anyone come across this issue or any suggestions on rectifying the same?

Thanks & Regards,
Rinsha

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