Subject: Re: [IBIS-Users] IBIS and HSPICE simulation result question
From: Gang Huo (ghuo@lsil.com)
Date: Tue Mar 26 2002 - 12:11:10 PST
Hi, All
Thank Jeremy for your response.
I should clear myself, the simulation with problem is a driver drive a
transmission then to the same I/O cell as the receiver. The simulation shows
good correlation when driving a open transmission line or a 50 Ohm load.
Well, I got a 'extreme currents present in GND clamp curve' warning when
running ibischk3 (around 30A). I know this is highly likely due to the
'perfect' diode with no intrinsic resistance in the HSPICE model per IBIS
cookbook. And the IBIS model may not correlate with the real buffer
performance, but I am surprised it did not correlate well with the HSPICE model
simulation in this case, since the IBIS model is derived from the same HSPICE
model I used.
Without further information on the diode information, is there a good way to
solve the problem? Will adding a small resistor with a fixed value (say 5-7
Ohm) do the trick?
Thanks in advance.
Huo,Gang
Jeremy Plunkett wrote:
> Gang,
> the IBIS model clamps will only affect the level of overshoot when the model
> you created is the receiver. If you are driving the model output into a
> transmission line test load, the level of overshoot at the end of the line
> will depend on the edge rate and output impedance of your IBIS model, but
> not on the clamps.
>
> I do a correlation check into a test load that matches the termination
> conditions that the driver will see in use, and correlate the waveform at
> _the driver's own output pad_ before looking at anything else. If the
> driver will be used on a terminated bus like DDR or GTL, use a test load
> that is a resistor equal to the transmission line impedance, connected to
> the termination voltage level. If the driver will be driving from the
> middle of a terminated bus, divide the transmission line impedance by two
> since the driver actually drives 2 transmission lines in parallel. If the
> driver will be used on unterminated lines, than the load should be a pullup
> or pulldown resistor equal to the nominal trace impedance.
>
> If your extraction was accurate, you should see near-perfect correlation of
> the output waveform into these loads. In particular, if you do a
> correlation into the same loads that are used for the IBIS model VT curves
> (usually 50 ohms pullup and pulldown), and you don't see 99% perfect
> correlation, then there is definitely a problem with either the model or
> your simulation setup.
>
> Good luck, hope this helped!
>
> Jeremy
>
> |>--/\/\/--((((((((()--|>
>
> Jeremy Plunkett
> Signal Integrity Engineer
> ServerWorks Corp
> www.serverworks.com
>
> |>--/\/\/--((((((((()--|>
>
> -----Original Message-----
> From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On Behalf Of
> Gang Huo
> Sent: Monday, March 25, 2002 12:47 PM
> To: ibis-users@eda.org
> Subject: [IBIS-Users] IBIS and HSPICE simulation result question
>
> Hi All,
>
> When I try to correlate a IBIS I/O model simulation with HSPICE model
> using HSPICE version 2000.4, the result is pretty good on the standard
> load and open transmission line load. One thing concerns me is that in
> the simulation of a load of transmission line to receiver simulation,
> the overshoot level of the signal is much higher when using the IBIS
> model than the HSPICE model, (the difference between two case is 0.5V
> nominal and 0.7V in best case, this is a 3.3v I/O buffer).
>
> I doubt this may be because of the clamp tables in the IBIS model. But
> as the creator of the model, I am pretty confident that the clamp tables
> in the IBIS model are correct, so can someone give me an idea what else
> in the IBIS model may cause this? Will this cause a problem to the
> users? And is there any good way to address this issue when creating the
> models?
>
> Thanks in advance,
> Gang Huo
>
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