Subject: RE: [IBIS-Users] Questions about Bus Hold (2nd try)
From: Muranyi, Arpad (arpad.muranyi@intel.com)
Date: Tue Nov 12 2002 - 08:56:51 PST
Rob,
I am a little bit confused about what you want to do. Here is why:
The intent of having the bus hold submodels was to make it possible
to simulate a structure in which two inverters are connected back to back
so that the first inverter's input is tied to the second inverter's output
which is also the die pad. (The two inverters are connected in series,
i.e. the output of the first stage is connected to the input of the
second stage).
This structure can be used as a receiver, or it can be connected
parallel with an I/O buffer. Either way, it works effectively as
a termination to the line, except it doesn't draw a lot of DC current
while the signal is held in one state or the other for a long time
because it switches to the same state. The only criteria you need to
watch is that the buffer that drives the signal must be stronger than
this hold circuit, so that it can pull it out of one state and push it
into the other state when a transition is happening.
So, the pad is driven by the second inverter, and you can model it with
normal IBIS modeling techniques. However, in order to get it's IV curves
you may want to remove the loop and tie the input of the first inverter
to high or low so that it doesn't switch while you are sweeping the IV
curve. Then you would also want to make Vt curves, which you would do
by applying the waveform that this device usually gets on the pad to the
input of the first stage. Using R_fixture and V_ficture on the output
of the second stage you get the IBIS waveforms. The only additional
thing you need are the threshold voltages that tells the simulator when to
start switching (this is basically the same as finding the actual Vinh and
Vinl for the first inverter).
From this you can see that the clamps are not the most important part of
this kind of a submodel, so I am not sure why those models you have seen
use clamps to describe the bus hold characteristics.
Now, if you are talking about the "Dynamic clamp" submodels than it is
the clamps that are of interest, but you didn't ask about that, so I won't
go into that for now.
I know I didn't answer all of your questions, but I wanted to clarify this
first. Once we are in synch on this we can go to the rest of your questions
(if you still have any).
Arpad Muranyi
Intel Corporation
==============================================================================
-----Original Message-----
From: rob.mataheroe@philips.com [mailto:rob.mataheroe@philips.com]
Sent: Tuesday, November 12, 2002 7:25 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] Questions about Bus Hold (2nd try)
Hello Ibis collegues,
I want to make accurate IBIS models for input buffers and I/O buffers with bus hold.
Existing models, I have seen on the web, show the bus hold characteristic in the ground clamp curve.
When running the IBIS checker, this causes non-monotonic warnings.
Therefore I am not sure whether this way of modeling is correct.
This brings me to the following questions:
1. If the bushold characteristic is present in the ground clamp curve, how would you qualify this:
1a Wrong, since it causes non-monotonic warnings
1b. Useless
1c. Okay, since it represents the actual behavior.
1d. Other ....
2. The IBIS standard describes the Bus Hold Submodel.
I assume the Top Model describes the buffer without bus hold characteristic.
From the IBIS standard I cannot understand what part of the circuit I must simulate in order to gather the data for the Bus Hold Submodel, namely the pullup, pulldown and last but not least the ramp figures.
Of course those who have designed the IBIS standard must know the idea behind the Submodel.
Therefore I would appreciate it very much if somebody could tell me:
2.1 Which part of the circuit is described by the sub model?
2.2 How can I get more information about this subject?
Thank you in anticipation for your reactions.
Kind regards,
Rob
________________________________________________________
Rob Mataheroe Philips Semiconductors bv
P.G. Logic Product Group PD&S Building AM1.108
Senior Design Modeling Engineer Gerstweg 2
Tel. ++31 (0)24 353 2370 6534 AE Nijmegen
Fax. ++31 (0)24 353 2820 The Netherlands
Email: Rob.Mataheroe@philips.com
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