Subject: Re: [IBIS-Users] Questions Regarding Bird 75.8
From: Al Davis (aldavis@ieee.org)
Date: Wed Jan 08 2003 - 00:36:15 PST
Can someone please post examples of mixed IBIS-Spice,
IBIS-Verilog, and IBIS-VHDL models so we can review them?
I asked for this several times before and so far have gotten no
useful responses. If the proponents of this BIRD are serious,
they will have made some examples manually to demonstrate the
concept. It is only by doing so that you can know enough about
it to proceed further.
I agree with the need, but I agree with Timothy that this
approach is confusing. I further believe that it doesn't even
come close to solving the problem that it is intended to solve.
The examples should demonstrate that it works, and is superior
to a Spice only (or *-AMS only) approach.
If such examples cannot be produced and published, it should be
rejected. It is the responsibility of those who think it is
good to prove it.
The proponents should also be able to explain:
1. How this impacts simulators that use only the [Model]
portion of an IBIS file. (not [Component])
2. How it is superior to documenting an equivalence between the
languages, like the equivalence between Spice and Verilog-A is
documented.
3. How it impacts mixed-mode simulators.
4. How such a model can be developed and tested.
If these questions cannot be adequately answered in this public
forum, it should be rejected.
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