Subject: RE: [IBIS-Users] RE: Vinh and Vinl definition
From: Henrik G. Madsen (hgm@vitesse.com)
Date: Fri Jun 20 2003 - 01:26:39 PDT
Hi,
There is actually a third option.
For single ended HSTL inputs, the HSTL standard specifies 0.75 V (Vref) as reference point for input waveform timing. Likewise VDDQ/2 for output timing.
Regards,
/Henrik
-----Original Message-----
From: Beal, Weston [mailto:weston_beal@mentorg.com]
Sent: 20. juni 2003 01:59
To: 'Eric Hsu'; Ibis-Users (E-mail)
Cc: Frank Dunlap
Subject: [IBIS-Users] RE: Vinh and Vinl definition
Eric,
If you intend to use the IBIS model for timing simulation then use the (ac) levels. If you are going to do noise measurements then you use the (dc) levels. For the general case I would include two sets of Vinl and Vinh with comments defining when to use each set.
In IBIS 4.0 you can specify all 4 levels directly in the [Receiver Thresholds] block, but I don't know of any simulation checker that recognizes those parameters, yet.
Regards,
Weston
> -----Original Message-----
> From: Eric Hsu [mailto:ehsu@netlogicmicro.com]
> Sent: Thursday, June 19, 2003 4:43 PM
> To: Ibis-Users (E-mail)
> Cc: Frank Dunlap
> Subject: Vinh and Vinl definition
>
> Hi IBIS experts,
>
> When reading HSTL spec. of JEDEC, it define Vinh(dc) and Vinl(dc) as Vref+/-100mV, Vinh(ac) and Vinl(ac) as Vref+/-200mV. For ibis model, which one it suppose to be taken?
>
> Best Regards,
>
> Eric Hsu
> Interface Technologies
> NetLogic Microsystems, Inc.
> 450 National Ave.
> Mountain View, CA 94043
> 650-961-6676 x198
> This e-mail contains NetLogic Microsystems, Inc. Confidential information
>
>
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