Subject: RE: [IBIS-Users] C-Comp
From: Roy Leventhal (Roy.Leventhal@ieee.org)
Date: Fri Jul 18 2003 - 08:38:04 PDT
Anshuli,
Be aware that capacitive behavior is included in the V-T behavioral curves
and/or the slew rates based on them. Unsophisticated providers of simulation
software (hopefully, few remain) can thus mistakenly "double count" the
effects of Ccomp unless they adjust for its presence in the circuit.
So, why is Ccomp included? To account for the capacitive loading on the
circuit, direct or reflected wave, and it is the total capacitive loading
looking into the die pad.
Best Regards,
Roy
-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On
Behalf Of Anshuli Goel
Sent: Friday, July 18, 2003 8:16 AM
To: 'ibis-users@eda.org'
Subject: [IBIS-Users] C-Comp
Hello Experts
I have one naive question.
While defining the C_Comp we say "C_comp defines the silicon die
capacitance. This value should not include capacitance of
the package.The C_comp capacitance must represent what you see when you
look into the die at the die pad. This includes the die pad, metal
connections on the die, the driver transistor's capacitance, the receiver
(input)capacitance, everything that is on the die."
But my understanding is that anyway the netlist is going to have driver
transistors in it in case of buffers, why do we need to account for the
capacitance for driver transistors ?? I can understand about the metal
connection and bond pad capacitance ,but I am not able to understand the
Transistors Capacitance part of it . Please clarify.
Regards
Anshuli
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