RE: [IBIS-Users] V-t curves offset

There is no common definition of "Time=0" between SPICE and various SI
simulators; the apparent delay through a buffer can be different in
different SI simulators. (This is not just a difference between SPICE and
IBIS.) This is why one simulates with the reference load to calibrate delay
calculations.

SPICE netlists often include logic (such as an inverter or MUX) ahead of the
I/O buffer input, so the SPICE simulation TIME and the time from the start
of the buffer's input toggling are not the same. Many model makers do not
subtract out the difference.

Sometimes a netlist puts more than one transition into a simulation, leading
to long delays before the start of the second transition (20-100 nsec is not
uncommon). Again, these times are often not subtracted out when generating
the V-t tables. (And this usually results in slower SPICE simulation than
running each transition as a separate simulation.)

Hope this helps.

- Lynne

"IBIS training when you need it, where you need it."

Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
lgreen22@mindspring.com

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of RODRIGUEZ_LECONA_RAMIRO
Sent: Tuesday, October 12, 2004 5:36 PM
To: ibis-info@eda.org; ibis-users@eda.org
Subject: [IBIS-Users] V-t curves offset

Hi all,

     I'm working with IBIS models validation and I have a problem
correlating the IBIS model with transistor level buffer in HSPICE. I
simulate both buffers with the same conditions (same load, temperature,
voltage supply) and the rising/falling edges of the outputs are equal but
there is a delay between IBIS model output waveform and transistor level
buffer output waveform. I shift the V-t Tables in the IBIS model to
compensate the delay and the output waveforms are matched but this occurs
when the input signal has rising/falling times equal to the rising/falling
times used to extract the IBIS model, if I use a input signal with
rising/falling times lower than the rising/falling times used to extract the

V-t curves then the buffer implemented with the IBIS model has again a
delay.
   What happens?
   How can I understand this? How can I avoid this delay?
   Or this phenomenom is normal because the important thing is the edge
waveform (buffer switching behavior) and the delay obtained is not relevant?
   Or the V-t curves obtained with specyfic rise/fall times are only valid
to simulate buffers with input signals with the same rise/fall times ?

   Thanks.

   Regards.

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Received on Tue Oct 12 21:34:39 2004