RE: [IBIS-Users] V-t curves discussion

To expand on a point raised in Jeremy's response, neither IBIS 4.0 or
its previous revisions includes any direct reference to the core-side
controls of the buffer. These are assumed to be defined and controlled
by individual tools. IBIS 4.1, through the VHDL-AMS and Verilog-AMS
multi-lingual extensions, *does* directly define *digital* ports for
buffer models. In this way, one could use a true digital logic input
stimulus pattern to control the output switching behavior of a driver.
Similarly, one could define analog control ports for models written in
Berkeley SPICE code, using the IBIS 4.1 D_to_A and A_to_D features.

- Michael Mirmak
  Intel Corp.
  Chair, EIA IBIS Open Forum

-----Original Message-----
From: owner-ibis-info@eda.org [mailto:owner-ibis-info@eda.org] On Behalf
Of Jeremy Plunkett
Sent: Friday, October 15, 2004 7:35 PM
To: RODRIGUEZ_LECONA_RAMIRO; ibis-info@eda.org; ibis-users@eda.org
Subject: RE: [IBIS-Users] V-t curves discussion

Ramiro,
there is no intent in the IBIS specification to model the behavior of
the
"core logic" side of the buffer. Most simulators provide facilites to
allow
driving the buffer model high, driving it low, and in some cases
tri-stating, although last I checked Hspice at least did a crummy job of
that (ignoring the Vt curves when transitioning to tristate). You can
consider it something of a "bonus feature" that in hspice the stimulus
input
to the buffer model is under your control and can be interfaced to other
circuitry if you wish to do so.

To take advantage of this, you need to scale the input voltage seen by
the B
element to have symmetric switching relative to its thresholds. This is
easy to implement many different ways; a resistor divider or a voltage
controlled voltage source come to mind immediately. In addition to the
voltage scaling, you will need to adjust the timing between the B
element
and the original spice netlist to allow for the time required to reach
the
IBIS thresholds vs the spice input threshold (typically 50% of the core
voltage).

If you simply wish to drive the B element and the original spice netlist
with matched timing and there is no additional circuitry beyond the
voltage
sources providing the stimulus, then I suggest you use a 1v swing and a
very
fast transition time (say 1ps) for the stimulus to the B element, and an
appropriate (core voltage) swing and transition time for the spice
netlist,
with the relative delays adjusted so that the B element's 1ps input
transition occurs as the spice input crosses the 50% level.

If you implement the stimuli this way you should see pretty close to
matching duty cycle and output timing between the spice and IBIS
versions of
the buffer, assuming the Vt curves in the IBIS model were not modified
from
the original data recorded from the spice model. Other tools will
produce
the same result as long as they are set up to preserve the original Vt
curve
timing (not always the default).

regards,
Jeremy Plunkett

|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email majordomo@eda.org
|with just the appropriate command message(s) in the body:
|
| help
| subscribe ibis <optional e-mail address, if different>
| subscribe ibis-users <optional e-mail address, if different>
| unsubscribe ibis <optional e-mail address, if different>
| unsubscribe ibis-users <optional e-mail address, if different>
|
|or email a written request to ibis-request@eda.org.
|
|IBIS reflector archives exist under:
|
| http://www.eda.org/pub/ibis/email_archive/ Recent
| http://www.eda.org/pub/ibis/users_archive/ Recent
| http://www.eda.org/pub/ibis/email/ E-mail since 1993
Received on Mon Oct 18 15:40:59 2004