RE: [IBIS-Users] Qn on V-t tables

Sivaram,

The buffer is modeled separately from the package. The IV and Vt curves
of an IBIS model represent what is in the buffer, on the die. The
package
model is a circuit that connects the buffer model with the rest of the
motherboard transmission line models.

Putting a package model between the buffer and the mother board is no
different from putting a connector model between two transmission line
models on the board.

Arpad Muranyi
Intel Corporation
=====================================================================

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of sivaram
Sent: Tuesday, October 19, 2004 6:47 AM
To: ibis-info@eda.org; ibis-users@eda.org
Subject: [IBIS-Users] Qn on V-t tables

Hi all,
   Would anyone of you,please, clear my doubts on V-t tables?

1) While generating IBIS file for a buffer,we get the v-t tables for
different load conditions (like Vcc, gnd etc).But we dont include
package parasitics in these simulations.
2) If case (1) is valid, are we correctly capturing the v-t
waveform?since we are neglecting the package parasitics in this
simulation.
3) Now,if we want to simulate this buffer(with the IBIS file) with the
package parasitics,what'll the simulator do with different v-t curves?
Will the simulator come up with a single characteristic behaviour using
different v-t curves?
One answer may be the simulator will get the voltage point for that
particular load and carry on the simulation with the parasitics.
But in reality,"we connect the load at the pin and not before the
package parasitics"

Please answer my cases (2) & (3)

Thanks
Sivaram

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Received on Tue Oct 19 15:52:04 2004