[IBIS-Users] Comments on 18 teleconference BIRD95.

Hello IBIS users.

 

BIRD 95: 

(I noted this in the conference but I think I wasn't understood.)

The SSN effect on timing is very important in system simulations. In the
IBIS summit we had seen some presentations about BIRD 95 and his ability
to model correctly the power bounce on the vdd pin.

I think this is very important but also important is the influence on
the buffer output signal in terms of delay and edge rate degradation.
Arpad has raised this at the end of the BIRD 95 discussion in the summit
(gate modulation effect). I think that we should consider adding more
effects that are due to pre-drive circuit and can influence the buffer
output. Gate modulation is one of the effects. But pre driver can suffer
from voltage drop in many ways such as: added delay to his logic
circuit, driving less then a complete '0' or '1' example: when having a
one buffer driving opposite pattern in a bus. When this buffer is trying
to drive high, the rest of the bus drives low. As a result there is a
ground bounce which affects the buffer (the single one) pre drive (the
pre drive last stage drives opposite then the buffer - the single buffer
drive high so his pre-drive drives low). Instead of the pre drive
driving 0 its driving something above 0 due to the ground bounce noise
and we get a wicker drive strength and probably different delay in the
output pin.

 

My point is: since IBIS 2.1 spec (and v(t) curves) we have 3 cases when
the buffer behavior is capture (under the assumption of ideal power
supply).This 3 cases are correct in term of pad delay due nominal
voltage changes (as describe in the ibis file). The delay information
was in the v(t) curves relations.  I think that when stepping forward to
SSO we need to ensure that the timing effect on the pads output is
capture within the IBIS (and this should be general enough to capture
all effects).

This is open for comments.

 

--
Regards
 
Itzik Peleg
Board Technology Group
 
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