Hi Fabio, As wang said, IBIS models has a limitation of producing I/O behavior at higher clock frequencies. you could be hitting this max limit way less than what you can achieve, because of improper modeling of the V-T tables. Some of the potential problem are 1: large lead time( initial stable time) 2: Large final dead time ( stable) Some simulator can handle this situation. I have observed that Buffer element in HSPICE-2008 and later versions can handle this situation. If your tool cannot handle it. You can modify VT tables as discussed in the file attached. There is one more discussion on the same point, you can find it on the IBIS quality specifications webpage. My suggest is ( go one by one) 1: Cut down all unwanted dead time. 2: You can try cutting down same amount of LEAD time from all V-T tables( both Rising and falling), better if it is same for all corners. 3: if you want to still more improvement, You can have different lead time for different corners. This can result in VT waveforms looking weird ( all corners waveform overlapping ), but make a note of the cause in NOTE field . ( NOTE : if you get required improvement at any of the stage stop there. Because in each stage you move a step way from conventional) This can help you in attaining maximum possible frequency of operation. Thanks, Muniswar From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Lance Wang Sent: Wednesday, March 18, 2009 1:35 AM To: ibis-users@eda.org; ibis@eda.org Subject: RE: [IBIS-Users] RE: [IBIS] input signal for model usage Fabio, There is another situation could be for the second point. Sometimes, when you compare the waveforms from Spice transistor-level simulations or measurements and waveforms that from the IBIS model simulations, you will find the differences. It could be happened that you are using faster input clock frequency. The reason is that IBIS model has the limitations or say your IBIS simulator has the limitations. So Arpad is right, you can not fix it for recapturing the VT curves. But sometimes it doesn't mean you buffer can not handle this kind of clock frequency. It could be just the limitations of your IBIS model or simulators. Regards, Lance Wang 978-764-2298 IO Methodology Inc. ________________________________ From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Muranyi, Arpad Sent: Tuesday, March 17, 2009 12:16 PM To: ibis-users@server.eda.org; ibis@server.eda.org Subject: RE: [IBIS-Users] RE: [IBIS] input signal for model usage Fabio, You are correct on the first one, and almost correct on the second. 1) The edge rate of the stimulus to an IBIS model will not change its output edge rate, but it will shift it, depending on how the tool implements the threshold on the stimulus input of the IBIS model. This is not related to the IBIS Vinh and Vinl (or related) parameters. The IBIS specification doesn't say anything about how the threshold of the input stimulus should be detected by the IBIS model implementation. 2) If you clock the IBIS model faster than the V-t curve can handle it you would need to make a new model, but not only a new model, but also a new chip. The fact that a V-t curve goes only so fast indicates that the chip itself can't go faster. So no matter how hard you try to make a new set of V-t curves, you won't succeed unless you redesign the chip itself... Arpad ============================================================= ________________________________ From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On Behalf Of Fabio BRINA Sent: Tuesday, March 17, 2009 8:00 AM To: 'Muniswara Reddy Vorugu'; ibis-users@server.eda.org; ibis@server.eda.org Subject: RE: [IBIS-Users] RE: [IBIS] input signal for model usage Thank you Muniswar, could you confirm (or correct) these propositions? : - if I change only rise/fall slew at the input (A_in as you say) the Output response is the same. (could be only a little shift time in the Output?) - if I change the input clock frequency (fck), the Output response is correct until fck is under the frequency used in the V-T tables generation. (if I want to use an higher clock frequency, I have to generate a new model with differents V-T tables) are that right? many thanks, Fabio ________________________________ From: owner-ibis-users@server.eda.org [mailto:owner-ibis-users@server.eda.org] On Behalf Of Muniswara Reddy Vorugu Sent: Tuesday, March 17, 2009 12:00 PM To: Fabio BRINA; ibis-users@server.eda.org; ibis@server.eda.org Subject: [IBIS-Users] RE: [IBIS] input signal for model usage Hi, The OUTPUT of I/O ( IBIS model) does not depend on the Rise/Fall slew at the input of I/O ( say A_in ). If you mean. Can you have different LOW/HIGH duration? You can give different clock/pulse frequency, but there is an upper limit of the clock. The upper limit of the clock frequency is limited by the duration of the V-T tables/Ramp time. Thanks, Muniswar From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Fabio BRINA Sent: Tuesday, March 17, 2009 3:55 PM To: ibis-users@eda.org; ibis@eda.org Subject: [IBIS] input signal for model usage Hello IBIS experts, Once an IBIS model has been created, can be used in different Input speeds? In other words: if I consider an I/O model, Can I use every input Pulse with several rise/fall time Or I have to use only the same pulse used in the model creations? I hope is clear what I mean. Thanks, Fabio -- This message has been scanned for viruses and dangerous content by MailScanner <http://www.mailscanner.info/> , and is believed to be clean. -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. 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