RE: [IBIS-Users] V-t graphs look for IBIS models

The IBIS Quality Specification has rules related to this:

5.4.2. {LEVEL 2} V-T tables have reasonable point distribution

V-T tables should be well behaved, with continuous second derivative.
V-T point density should be

sufficient in areas with non-zero second derivative. For example, a low
to high state transition

should have at least 10 points.

This check is easily accomplished by viewing the curves and checking
visually.

5.4.3. {LEVEL 3} V-T table duration is not excessive

To avoid the "over clocking" issue, excess V-T points may be removed to
match the V-T duration

corresponding to the maximum data rate or frequency at which the device
is expected to operate.

When removing trailing V-T points the final DC value must be achieved,
i.e., the ending slope

should be very small. Since the two sets of V-T tables describe the
relative on and off switching

delay between the pullup and pulldown transistors, relative time
position between all tables with

the same edge direction and corner must be maintained when removing the
leading excess V-T

points. The number of excess V-T points removed can be different between
corners (i.e., Typical,

Minimum and Maximum) but it is recommended to explain the difference as
comments of the IBIS

file.

5.4.4. {LEVEL 2} V-T table endpoints match fixture voltages

If the V_fixture values equal the supply reference voltages for the
[Pullup] or [Pulldown] tables,

then either the starting or ending points of the V-T tables are expected
to equal these V_fixture

values. This applies to full swing technologies such as CMOS, and not to
technologies such as

TTL, PECL, LVDS, or SERDES driver, which do not necessarily swing rail
to rail. This check

does not apply in cases where internal pullups/pulldowns or bias
conditions exist such that the

combined I-V tables have current flows at the V_fixture voltages.

For example for a 3.3 V device with the [Voltage Range] set to 3.3 V,
V_fixture = 3.3 V, and

R_fixture = 50 ohms, the [Rising Waveform] table should end at 3.3 V,
and the [Falling

Waveform] table should begin at 3.3 V.

However, numeric limits are not given. I have been using 50% as the
minimum portion of a V-T curve that the edge transition should fill,
where the beginning and end of a transition is based on a 20mV/s dV/dt
threshold. I use an overall Ttransition/Ttotal metric instead of
limiting leading and trailing times separately. Now and then I get
curves slightly under 50% on perfectly reasonable models, so 1/3 may be
a good rule too.

The 10 points minimum in the transition rule is slightly more
troublesome, as many models fall short or barely have that many. I'm
using the same 20mV/s threshold to define the beginning and end of the
transition, and I generously count one point before and one after the
transition. Quite a few models still don't have 10. I think edge times
are getting smaller faster than we are reducing our IBIS waveform
generation parameters.

If the formatting of the IQ rules above is a problem see
http://www.eda.org/ibis/quality_ver2.0/quality_ver2_0.pdf

Mike LaBonte

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of Baker, Bonnie
Sent: Wednesday, May 26, 2010 6:40 PM
To: ibis-users@eda.org
Subject: [IBIS-Users] V-t graphs look for IBIS models

During the QC review of our IBIS models, we had a short discussion about
the basic format of the V-t graphics. There are a few things that we
know

1. The curves should not end too soon, meaning that they have not
finished settling to their final DC value.
2. The end points should be consistent with the IV curves.
3. There are more points where the slope in changing (at least 10
points during the transitions)
4. The lead time into the V-t Table is minimized

What we don't know is if there is recommended ratio between the time
that the curve is transitioning from high to low (or low to high) versus
the time that the curve is at its final DC value? For instance, I am
recommending the approximate relationship of 1/3 to the time in
transition and 2/3 of the time at a final stabilized DC value for the
worst case curve (between the rising and falling curves).

Any thoughts?

Best Regards,

Bonnie Baker

Sr. Applications Engineer

Texas Instruments, Tucson

5411 E. Williams

Tucson, Arizona 85711

(520) 750-2116 (work)

(520) 548-3111 (cell)

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