[IBIS-Users] Asian IBIS Summit (Taiwan) - Fourth Announcement

From: Bob Ross <bob@teraspeed.com>
Date: Fri Oct 08 2010 - 10:35:42 PDT

To All:

The IBIS Open Forum is holding an Asian IBIS Summit Meeting in
Taipei, Taiwan a major technology center on Friday, November 12, 2010.

Up to 8 presentations or topics are listed below. A few more are
expected. Several of these will be given at the other Asian Summits.

Several companies listed below are co-sponsoring this major event
to be held at the Sherwood Hotel, Taipei. We are planning for
many local attendees and also several IBIS experts from the USA.

We encourage technical contributions from Asia. We expect a full
agenda of relevant material.

Note we are also holding these Asian IBIS Summit meetings:

   Shenzhen, P.R. China, Tuesday November 9, Four Points Hotel
   Tokyo, Japan, Monday, November 15, JEITA headquarters

Bob Ross
Teraspeed Consulting Group

Polin Chi
Sigrity

-----------------------------------------------------------------------
                          ASIAN IBIS SUMMIT (TAIWAN)
                               FOURTH CALL FOR
                       PARTICIPATION AND PRESENTATIONS
-----------------------------------------------------------------------

             A S I A N I B I S S U M M I T ( T A I W A N )

Time/Date: Friday, November 12, 2010, 8:00 to 16:30 (date correction)
             Meeting starts at 8:30 AM

Location: Sherwood Hotel
             11 Min Sheng E Road, Sec. 3
             Taipei, Taiwan

Rooms: Ballroom I and II

Content: Presentations and Discussions

Purpose: Solicit and exchange IBIS and interconnect model related
             information and ideas.

Co-sponsors (in alphabetical order):
             Agilent Technologies
             Avant Technology (IO Methodology)
             Foxconn
             ICT-Lanto
             Intel Corporation
             Sigrity
             Synopsys

Cost: FREE, including refreshments and buffet lunch

Vendors: Some vendors will have information tables outside
             the meeting room

             Contact us for details regarding sponsorship.

BACKGROUND

    We have held many successful Summit meetings across Asia in previous years.
    This year we are adding a meeting in Taipei where many national and
    international high technology companies have operations. Presentations
    from past events are available at our Summit archive:

      http://www.eda.org/pub/ibis/summits/

    Our objective is to reach out internationally to communicate with
    the local experts and to learn of regional concerns.

CONFERENCE LANGUAGE

    The conference language is English, but we will plan for technical
    translations in English and Chinese. So presenters can optionally
    deliver in Chinese as long as an English version of the material is
    available.

IBIS SUMMIT

    This meeting will be conducted as a formal IBIS Summit Meeting.
    Presentations will be archived in an electronic format on our
    Summits site, and minutes of the meeting will be issued. However,
    no formal decisions requiring votes will be planned.

CALL FOR PARTICIPANTS

    People involved in IBIS and interconnect model development, EDA
    tool development, and digital circuit design are invited to
    participate in the Summit meeting. If you plan to participate,
    please register using the information below (in English):

      Name:
      E-mail address:

      Company:
      Top-level Web Link:

      Country:
      Telephone:

      Comments:

    Send to BOTH:

      Bob Ross, Teraspeed Consulting Group bob@teraspeed.com
      Polin Chi, Sigrity polinchi@sigrity.com

    SIGNUP DEADLINE: November 4, 2010

CALL FOR PRESENTATIONS

    We are seeking presentations from individuals who have IBIS and
    interconnect modeling experiences or issues. If we have to
    select presentations for the number of time slots available, we
    will give preferential consideration to presentations from Asia.

    Presentation Format: LCD Projection from meeting laptop computer

    Time: 15-30 Minutes including questions

    Electronic Archival: All presentations will uploaded to our public
                           IBIS Summit archives

    Electronic Format: Power Point or Acrobat

    Presentation Booklet: Available at the meeting for all attendees

    Presentation Deadline: October 22, 2010 to produce the presentation
                           copies for the meeting

    If you plan a presentation, please ADD to the above registration
    information:

      Title of Presentation:

      Estimated Time:
        (30 minutes or less)

    We will notify you of acceptance and may follow up with questions
    when we form the program agenda.

    Note: Vendor promotional or business information is prohibited.
    We review all submitted presentations and may request modifications.
    Submitted presentations must be in English, although the delivery
    can be in Chinese.

    Submissions from Taiwan and across Asia are strongly encouraged,
    though submissions from other regions are very welcome. Topics may
    include behavioral modeling of buffers, interconnects or other system
    components.

AGENDA

    8:00 - 8:30 Vendor table setup and tables
    8:00 - 8:30 Sign in
    8:30 - 12:00 Presentations
    12:00 - 13:30 Free buffet lunch, vendor tables
    13:30 - 16:30 Presentations

    The specific agenda is being developed. We expect nine or ten
    presentations covering a range of issues from existing customer
    experiences, existing clarifications and some of the future
    directions in IBIS to deal with technical advances.

    Several major IBIS Committee presentations from IBIS officers or
    active members are planned.

    Several presentations on IBIS applications and behavioral modeling
    issues, including interconnects and system components, are expected
    from co-sponsor companies and/or their customers.

    Tentative Titles or Topics:

    Intel Corporation:
      IBIS Chair Introduction topic
      IBIS-ISS topic
    Foxconn
      "Enforced Passivity of S-Parameter Sampled Frequency Data"
    IO Methodology:
      "Point Reduction Method for IBIS Curves"
    Cadence Design Systems and Sigrity:
      "Model Connection Protocol Extensions for Mixed Signal SiP"
    Flextronics and Cadence Design Systems:
      "Extending/Leveraging IBIS Constructs to Model High-Speed I/Os
      and Packages using AMI, Spice, and S-Parameters"
    Sigrity and Huawei Technologies:
      "Spice Sub-circuit Support for Serial Link Channel Design by Using
      IBIS [External Model]"
    Micron Technology:
      C_pin Measurement Correlation topic

LIST OF NEARBY HOTELS AND TRAVEL RULES

    Hotels in all price ranges can be found through internet searches.

-----------------------------------------------------------------

-- 
Bob Ross
Teraspeed Consulting Group LLC     Teraspeed Labs
121 North River Drive              13610 SW Harness Lane
Narragansett, RI 02882             Beaverton, OR 97008
401-284-1827                       503-430-1065
http://www.teraspeed.com           503-246-8048 Direct
bob@teraspeed.com
Teraspeed is a registered service mark of Teraspeed Consulting Group LLC
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Received on Fri Oct 8 10:35:56 2010

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