[IBIS-Users] Asian IBIS Summit (Taipei) - Agenda

From: Bob Ross <bob@teraspeed.com>
Date: Thu Nov 10 2011 - 17:21:48 PST

All:

 

We have a full program with nine presentations and registration

nearly filled to capacity. We are looking forward to seeing everyone

in Taipei.

 

Best Regards,

Bob and Polin

 

------------------------------------------------------------------

 

       A S I A N I B I S S U M M I T I N F O R M A T I O N

 

Time/Date: 8:00 - 16:30, Friday November 21, 2011

 

Location: Sherwood Hotel

            111 Min Sheng E Road

            Sec.3, Taipei, Taiwan

 

Rooms: Ballrooms I and II (3rd Floor, look for signs)

 

Sponsors: Avant Technology (IO Methodology)

            Cadence Design Systems

            Foxconn Technology Group

            Intel Corporation

            Sigrity

            Synopsys

 

------------------------------------------------------------------

 

          I B I S S U M M I T M E E T I N G A G E N D A

 

8:15 REFRESHMENTS & SIGN IN

           - Vendor Tables Open at 8:30

 

9:00 Welcome

          - Sogo Hsu

            (Foxconn Technology Group, ROC)

          - Michael Mirmak

            (Chair IBIS Open Forum, Intel Corporation, USA)

 

9:20 IBIS Status and Future Direction

          Michael Mirmak (Intel Corporation, USA)

 

9:35 IBIS Parsers

          Bob Ross (Teraspeed Consulting Group, USA)

 

10:05 BREAK (Refreshments and Vendor Tables)

 

10:25 Power Aware Features of IBISv5.0 - Accuracy and Challenges

          Vipul Pursottam Patel, Prabhat Ranjan, and Richa Ahuja

          (STMicroelectronics, India)

 

10:55 Modeling the On-die De-cap of IBIS 5.0 PDN-aware Buffers

          Lance Wang* and Randy Wolff**

          (*IO Methodology, and **Micron Technology, USA)

 

11:25 Power-aware I/O Modeling for High-speed Parallel Bus Simulation

          Jack W.C. Lin#, ZuLi Qin##, HaiSan Wang##, and

          Raymond Y.Chen### (Sigrity, #ROC, ##PRC, ###USA)

 

12:00 FREE BUFFET LUNCH (Hosted by Sponsors)

          - Vendor Tables

 

13:30 Board-only Power Delivery Prediction for Voltage Regulator

        and Mother Board Designs

          Jiangqi He# and Y.L. Li## (Intel Corporation, #USA, ##ROC)

 

14:15 Supporting External Circuit as Spice or S-parameters in

        Conjunction with I-V/V-T Tables

          Kent Drumstad*#, Adge Hawes*##, Taranjit Kukal**###,

          Feras Al-Hawari**#, Ambrish Varma**#, and Terry Jernberg**#

          (*IBM, #USA, ##United Kingdom, **Cadence Design

          Systems, ###India, #USA)

 

15:00 BREAK (Refreshments and Vendor Tables)

 

15:20 T-Coils and Bridged-T Networks

          Bob Ross (Teraspeed Consulting Group, USA)

 

16:00 Pseudo Transient Eye Analysis by Convolution Method

          Baolong Li (ANSYS, PRC)

          [Extra Presentation]

 

16;25 Concluding Items

 

16:30 END OF IBIS SUMMIT MEETING

 

------------------------------------------------------------------

 

To Register by November 15, 2011:

 

     Name:

     E-mail address:

 

     Company:

     Top-level Web Link:

 

     Country:

     Telephone:

 

   Send to BOTH:

 

     Bob Ross, Teraspeed Consulting Group bob@teraspeed.com

     Polin Chi, Sigrity polinchi@sigrity.com

 

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Received on Thu Nov 10 17:23:19 2011

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