Subject: Re: [IBIS] IBIS SUmmit minutes 6/13/02
From: Scott McMorrow (scott@teraspeed.com)
Date: Fri Jun 21 2002 - 18:58:40 PDT
Lynne and Hassan,
Here is my take on the leadinge edge "flat" zone.
>2) The model maker does not need to re-simulate to remove the
>leading and trailing "flat" zones. Rather, they need to remove any
>data that comes before the signal change into the buffer (such as the
>inverter chain in #1). They also need to remove the "flat" zone after
>the three V-t columns have stabilized. Only the model maker has
>enough information about how the model was simulated to make these
>changes safely.
>
>
>
Removal of the leading edge "flat" zone must be accomplished equally on
all curves. Exactly the same amount of leading edge data should be
removed from the min/typ/max VT curves. This is necessary to insure
that relative delay differences from slow to fast corner are still
incorporated in the curves so that accurate timing measurements can be
made. In quite a few cases, test load timing must be measured relative
to the slow device corner, irrespective of the corner that is being
simulated in the actual circuit, when Maximum timing is being
characterized and measured. Worst case slow timing, which is specified
by the manufacturer, should be used as the reference for system flight
time measurements at all corners. In order to accomplish this, the
delay between typ/min/max VT curves should remain constant after
processing of the leading edges.
When I create IBIS models I remove an equal amount of data points from
the leading edge of all waveform tables, up until the first waveform
transition. For the trailing edge flat zones, I adjust the extraction
time in Spice so that the slow process waveform "just" reaches final
value. In this way, the number of points in all curves is optimized for
maximum fidelity. This is very important in Version 3.2 models where a
compliant model can have only 100 points. In the worst case on 33
points are available to model the transition region of each waveform.
It does not make sense to have trailing edge flat points when do do so
takes points away from modeling the transition curves themselves.
For those who want to know how I accomplish this, I run spice2ibis on
the buffer at each corner with a long simulation time and then look at
the curves and measure where the last stable transition occurs in time.
Then I use that number is the simulation time for the final extraction run.
Regards,
scott
-- Scott McMorrow Teraspeed Consulting Group LLC 2926 SE Yamhill St. Portland, OR 97214 (503) 239-5536 http://www.teraspeed.com----------------------------------------------------------------- |For help or to subscribe/unsubscribe, email majordomo@eda.org |with the appropriate command message(s) in the body: | | help | subscribe ibis <optional e-mail address, if different> | subscribe ibis-users <optional e-mail address, if different> | unsubscribe ibis <optional e-mail address, if different> | unsubscribe ibis-users <optional e-mail address, if different> | |or email a request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993
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