Subject: Re: [IBIS] BIRD 75 comments
From: Ross, Bob (bob_ross@mentorg.com)
Date: Wed Aug 28 2002 - 20:05:11 PDT
Lynne:
Thank you for your comments. I am replying in your text to
your points and questions.
Bob Ross
Mentor Graphics
Lynne Green wrote:
>
> Great discussion thread so far. Arpad and Bob have
> addressed some major points in depth.
>
> Several keywords/subparameters we may want to keep,
> whichever way the BIRD decides to go:
> receiver thresholds
> Vmeas, Cref, Rref, Vref
> Enable polarity
> all of the various test fixtures, including golden waveforms
> Model_type
> voltage range (perhaps extend to Vss as well as Vcc).
> temperature range
> reference voltages, external reference
> [Ramp], because algorithms can use this to estimate
> the edge rate for various calculations.
Except for [Ramp], your ideas are similar to what is proposed.
Did you intend to leave out [Model Spec]?
>
> The suggestion of setting C_comp to 0pF if it is included in
> the external model leaves the model maker a choice of
> where to include it. Choice is good, unless it is confusing
> to the model maker.
>
> The "philosophy" appears to offer two choices:
> Put [External Model] under [Model], and list all the things that
> must NOT be included, or separate the two and list all the things
> that MUST and CAN be included. Any insight on which might
> be easier for a parser implementation?
Initially I think putting [External Model] under [Model] is
easier. The parser can treat three cases:
(a) Existing IBIS if [External Model] is ommitted.
(b) [External Model] with minimal existing IBIS subparameters
(c) [External Model] with full IBIS model data (by doing (a)
with all the lines between [External Model]/[End External Model]
skipped
>
> One new question: Can an [External Model] be used to replace
> a package model? This might be a way to address typ/min/max
> package variations in a complex package.
[External Model] was intended for extended model descriptions.
[External Circuit] was intended to be used for additional on-die
circuitry. It could be used for package descriptions in special
situations with the package model itself zeroed out. Because it
is defined for on-die usage, I would not recommend semiconductor
vendors to use it for package model descriptions in models that
they provide. This may conflict with how EDA tools might set up
internal test points.
>
> Best regards,
> Lynne
>
> Lynne Green
> Senior Member of Consulting Staff
> Cadence Design Systems, Inc.
>
> "All the world's an analog stage, whereon digital plays bit parts."
>
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