Subject: [IBIS] Revised minutes (01/27/03)
From: deBurgh, Guy (guy_deburgh@mentorg.com)
Date: Tue Feb 04 2003 - 09:04:44 PST
As a result of feedback the following two paragraphs have been updated:
- DATA DEPENDENT BUFFER CHARACTERISTICS
- AD HOC DISCUSSION
The remainder of the minutes remain the same.
My apologies,
Guy de Burgh
(IBIS secretary - retired)
DATE: 02/04/03
SUBJECT: January 27, 2003 EIA IBIS Summit Meeting Minutes
VOTING MEMBERS AND 2003 PARTICIPANTS LIST:
Ansoft Corporation (Eric Bracken)
Apple Computer Kim Helliwell*
Applied Simulation Technology Fred Balistreri*
Cadence Design Lynne Green*
Cisco Systems Syed Huq*, Val Mandruson*, Hung Pham*
Cypress Semiconductor (Rajesh Manapat)
Huawei Technologies (Jiang Xiang Zhong)
IBM (Pravin Patel)
Intel Corporation Stephen Peters*, Michael Mirmak*,
Arpad Muranyi*
LSI Logic Frank Gasparik
Matsushita (Panasonic) Atsuji Ito*
Mentor Graphics Bob Ross*, Ian Dodd*, Guy de Burgh,
John Angulo*, Mike Donnelly*, Weston Beal*
Micron Technology Randy Wolff
Mitsubishi (Pat Hefferan)
Molex Incorporated Gus Panella*
Motorola (Rick Kingen)
National Semiconductor Milt Schwartz*, Tim Coyle*
NEC Electric Corporation (Itsuki Yamada)
North East Systems Associates Edward Sayre*
Philips Semiconductor (D.C. Sessions)
Quantic EMC (Mike Ventham)
Siemens (& Automotive) AG (Eckhard Lenski)
Signal Integrity Software (Bob Haller), Barry Katz*, Doug Burns*
Sigrity Raj Raghuram*
SiQual (Rob Hinz)
Texas Instruments Thomas Fisher*
Teraspeed Scott McMorrow*, Tom Dagostino*,
Kevin Simpson*
Time Domain Analysis Systems Dima Smolyansky*, Steve Corey*
Via Technologies (Weber Chuang)
Zuken (& Incases) (Michael Schaeder)
OTHER PARTICIPANTS IN 2003:
Brocade Frank Yuan*, Yongrue Yu*
Conexant Gary Felker*
EMC Corporation Brian Arsenault*
Fujitsu Tadashi Arai*
GEIA (Chris Denham)
Hitachi ULSI Systems Kazuyoshi Shoji*
Independent Kelly Green*
NetLogic Microsystems Eric Hsu*
Plexus Joseph Socha*
Xilinx Susan Wu*
In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.
Upcoming Meetings: The bridge numbers for future IBIS teleconferences
are as follows:
Date Bridge Number Reservation # Passcode
February 14, 2003 (916) 356-2663 3 1805849
All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after. When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.
NOTE: "AR" = Action Required.
-------------------------------- MINUTES -----------------------------------
INTRODUCTIONS AND MEETING QUORUM
The IBIS Summit Meeting was held in Santa Clara, California at the Santa
Clara Convention Center. About 38 people representing 24 organizations
attended.
The notes below capture some of the content and discussions. The meeting
presentations and other material are uploaded at:
http://www.eda.org/pub/ibis/summits/jan03/
Stephen Peters opened the meeting and thanked DesignCon for providing the
meeting room and the booth space as part of our Associate Sponsorship of
DesignCon. He thanked Milt Schwartz and National Semiconductor for
providing
the hot lunch and arranging for paper copies of the presentations, and
Applied Simulation Technology for supplying the LCD projector.
He thanked Guy de Burgh and Mentor Graphics for providing and setting up the
IBIS booth #703 and for managing the collection of IBIS member company logo
plaques for the background. Finally, Stephen thanked Lynne Green of Cadence
Design for providing copies of the presentations, putting together the
agenda, and for overall logistical support.
Stephen asked everyone in the room to introduce themselves. The group was
well represented by semiconductor vendors and model providers, EDA tool
vendors, and users of IBIS models.
Stephen noted one change from the published agenda. Due to a conflict, Dima
Smolyansky's presentation was moved to 9:30am, trading places with Atsuji
Ito's presentation which was moved to 1:00pm. Finally, Stephen thanked the
presenters and participants for attending.
PRESENTATIONS AND DISCUSSION TOPICS
The rest of the meeting consisted of presentations and discussions. These
notes capture some of the content and discussion. More detail can be found
in the uploaded documents.
IBIS CHAIR REPORT
Stephen Peters, Intel Corp.
Stephen opened his presentation with a review of the day's events. Stephen
noted that IBIS Parser funding is on track, with a total of 9 companies
pledging support. Atul Agarwal has begun development of the parser itself.
In addition Kelly Green (an independent contractor) is developing an open
source parser for the Interconnect Modeling (ICM) specification. Stephen
mentioned that the IBIS Quality committee is going strong and that BIRD75
was passed, thus enabling multi-lingual modeling in IBIS.
Upcoming challenges for the year include moving towards IBIS4.1 and making
the ICM specification a reality. Stephen set a challenging goal of having
IBIS4.1 or IBIS4.2 ready for consideration as a standard by September of
2003. Finally, Stephen would also like to see an article about IBIS support
for multi-lingual modeling appear in one of the trade publications.
REFLECTIONS ON IBIS
Bob Ross, Mentor Graphics
Bob began his presentation by noting that IBIS started in 1993 with 10
members which included 9 EDA and 1 semiconductor company. Today our 31
members include 10 EDA companies, 10 semiconductor companies, and several
end users and consultants. However, Bob also mentioned that over the years
mergers and acquisitions have reduced the pool of potential supporting
companies, thus limiting our financial base. As an example, Mentor Graphics
now owns 9 parser licenses through acquisitions. This will be a concern as
IBIS moves forward. Bob also made the case that the industry has accepted
IBIS, as evidenced by SI reflector traffic and the fact that IBIS is being
mentioned in textbooks and industry references.
Bob noted that while IBIS has plusses and minuses, the bottom line is that
IBIS solved the industry problem of protecting IP while allowing "accurate
enough" simulations, and the format was something EDA tools and users could
handle. Affiliating with a formal standards body (the EIA) was the turning
point is getting semiconductor vendors to accept IBIS, and the Open Forum
format (welcoming contributions from members and non-members) helps build
support. Finally, Bob noted that we keep our cost per member low by
leveraging contributions from individuals and companies. In summary, Bob
emphasized that the industry has built major infrastructure around IBIS, and
that success exists when others promote IBIS.
Several attendees asked how many IBIS models were available for download.
While Bob did not have exact numbers, the consensus was the number of
publicly available models is in the thousands.
LOSSY LINE SIMULATION AND ANALYSIS
Dima Smolyansky, TDA Systems
Dima begin by noting that his presentation was based on an article he
authored for the upcoming March 2003 edition of Printed Circuit Design
magazine.
Dima stated that there are four basic ways of including interconnect
loss in a modeling and simulation environment: S-parameters, parametric
models, frequency tables and behavioral (lumped LRGC element) models. Dima
went on to describe the advantages and disadvantages of each.
S-parameter models are tried and true, and because they are measurement
based it is not necessary to create a detailed interconnect model.
However, not all SPICE type simulators support S-parameters. There is also
the question of simulation efficiency when combining non-linear drivers
with a linear interconnect. Parametric models are fast and efficient, but
the accuracy depends on the specific assumptions one makes about the
equations and parameters. Dima noted that with pre-defined assumptions
it is relatively easy to extract accurate models from measurement. Another
way to simulate loss is with a frequency table. These models can be very
accurate, but they simulate slower. Dima emphasized that both interpolation
and extrapolation errors are potentially large errors if they are not
handled properly. Finally, behavioral modeling (lumped element equivalent
circuit approach) is a good method if one wants to achieve exact correlation
between model and measured data. Also this is the only approach that can
guarantee passivity (non amplification) in the interconnect. However,
simulations using behavioral models tend to be slower than parametric
models. In summary, Dima stated that for simulating long cables or traces
parametric models were the best, but for shorter structures one can use more
exact behavioral models.
In the follow up questioning it was noted that some simulators have issues
with chaining S-parameters -- breaking an interconnect into smaller pieces
then simulating each piece and combining results does not give the same
answer as simulating the interconnect as one large lump. Several attendees
also asked how one could insure a simulator could insure passivity and
causality in their simulation. Dima replied that this is a tool specific
issue.
IBIS QUALITY COMMITTEE UPDATE / PRACTICAL USE OF IQ CHECKLIST
Barry Katz and Robert Haller, Signal Integrity Software (SiSoft)
Barry opened the presentation by noting that the goal of the quality
committee is to achieve models with no parser errors or warnings. The focus
over the past year has been the creation of a quality checklist and rating
system. Barry noted that the committee has 75 members on its mailing list
and has submitted at least 3 IBISCHK bugs.
Barry defined the quality levels as:
level 0 - passes IBISCHK and includes a few required keywords
level 1 - complete with all needed keywords and pin lists and data
for all three corners.
level 2a - models have been run through a simulator and correlated to a
transistor level model
level 2b - models have been correlated to bench measurements
In cases 2a and 2b above the correlation metric is based on the IBIS
Accuracy Handbook. The committee is now working on a document that explains
the various checklist items. In the following discussion on model quality
and creation, Scott McMorrow noted that because the s2ibis generation
program is free the perception is that model generation must be easy and
is thus devalued. In response to another question, Tom Dagostino mentioned
that models from measurement are the most accurate, and that it is possible
to create models from skewed silicon, or at least over VT corners.
Barry continued the presentation by illustrating how SiSoft uses the quality
checklist to provide complete model documentation. SiSoft starts with a
working SPICE model, then after generating the IBIS model compares
simulation results using the IBIS model with those obtained from the
transistor level model. The correlation and final report are based on
the IBIS Accuracy Handbook.
IBIS MODELING EXPERIENCES
Tim Coyle, National Semiconductor
Tim opened his presentation by noting that there are several different
methods for creating IBIS models of LVDS buffers and not every method works
for every LVDS device. The model creator has to understand the circuit
design (output structure) of the buffer being modeled. The biggest
difference between types is the presence of internal termination resistors,
which may or may not be supported by an EDA tool.
Scott McMorrow pointed out that at 10Gb/s buffers are differential and
operated in their linear region, thus it's rather easy to create a well
behaved and accurate model of the buffer itself. The difficulty lies in
creating accurate package models. Several folks noted that many IBIS
simulators do not support advanced package models and one often has to
create separate package models specific to the simulator tool. Ed Sayer
again emphasized the need to add header information that documents model
limits - especially with respect to the package.
In a related discussion on accuracy, Stephen Peters asked how EDA tools
differ on simulation results. The consensus is that waveform differences
are on the order of a few percent. The critical issue seems to be how the
package parameters are interpreted -- lumped or distributed. John Angulo
noted that the current EBD specification is clear on how package parameters
should be interpreted.
Finally, Tim announced that National Semiconductor has an IBIS modeling
resource web page, containing both technical white papers and short papers
on various issues. The URL is as follows:
http://www.national.com/appinfo/lvds/ibis_home
DATA DEPENDENT BUFFER CHARACTERISTICS
Arpad Muranyi, Intel Corporation
Arpad presented a case in which current IBIS is not capable of modeling an
effect seen in differential buffers with de-emphasis. Arpad explained that
de-emphasis is accomplished by ganging two differential drivers together
(one is stronger than the other) then controlling when they turn on or off.
An initial IBIS model was created by ganging two different IBIS models
together, each model representing one stage of the output. Each individual
model correlated well to the transistor model, but when the two IBIS models
were combined the result did not match the transistor level model output.
Specifically, the DC levels after transition did not match, and there were
large undershoots and edge rate mismatches. A re-extraction of the VT curves
from the combined SPICE model got rid of the undershoot, but the DC level
and
edge rate mismatch remained. After further investigation Arpad discovered
the problem was a transistor level phenomena with the individual current
sources for each differential driver stage. Due to Miller capacitance,
the output waveforms were coupled to the gate of the current source
transistor, modulating the effective drive strength of the buffer as a
function of the buffer driving normal or de-emphasized data. Arpad was able
to improve the model's final output waveforms with tedious fine tuning, but
he was not able to match all aspects of the edge rates and the DC level
mismatch problem.
The bottom line is that this effect is real, it cannot be modeled in
traditional IBIS, and therefore BIRD75 extensions are required.
LUNCH
THE CASE STUDY OF BOARD SIMULATION
Atsuji Ito, Matsushita Electric Industrial Co. Ltd. (Panasonic)
Atsuji began with a update on JEITA activities. JEITA is developing an EDA
Standards Dictionary. The purpose is to facilitate simulation, and the
dictionary includes circuit diagrams, specifications, characteristic
graphs, etc. They have received sample dictionaries from several companies
including Kyocera, Murata and TDK, and appliance makers have evaluated and
verified the dictionary. Feedback will be discussed at the next JEITA EDA
working group, and they hope to release the first version of the dictionary
at the end of June.
Atsuji then went into case study of board simulation usage on a digital TV
design. The use of simulation enabled the final product to be done with
three board turns (instead of five), and cost were down. Simulation also
enabled a DAC/ADC conversion from board to board to be removed. In this
case simulation was applied to connector pinout and placement. They also
used IBIS simulations to reduce a Rambus memory board from 6 to 4 layers.
However, Atsuji noted, there were issues. They would like to use time domain
simulations for digital sections of the board, but the high frequency
component models are specified using S-parameters. To get around this
problem Panasonic translates the S-parameter models to SPICE models. They
achieved fairly good results using this method, but they felt there needs
to be more work to understand the limitations and theoretical limits.
The next step is to expand the number of passive component modules
available.
Finally, Atsuji presented two issues he would like the IBIS Open Forum to
address. JEITA would like to see IBIS support more corners than the
current typ/min/max. They would also like closer cooperation between IBIS
and JEITA to improve the board simulation environment. Specifically, they
would like IBIS to concentrate on improving LSI package module model
accuracy.
IBIS INTERCONNECT SPECIFICATION (ICM): STATUS AND PROPOSED CHANGES
Kelly Green, Independent and Michael Mirmak, Intel Corp.
Michael Mirmak began by presenting a history and brief overview of the
structure of the ICM specification. The key point is that the draft ICM 1.0
specification needs some revision. Some changes involve typographical errors
and inconsistencies that survived the earlier revision process, other
changes are related to ease of software parsing. Michael noted that 17
changes are strictly editorial and have no impact on function. Twenty three
other changes are clarifications to provide stricter interpretation of
content. Most of these latter changes were found by the LEX/YACC parser.
Kelly Green then gave the group an update on the status of the ICM parser.
An ANSI C prototype is in development, and unless there are significant
changes Kelly expects the ICM parser code to be available in May. Kelly
noted that it took three weeks of work with FLEX and YACC/BISON to enable
the parser to determine if a file is correctly structured. He is
looking at another month for semantic analysis. A question was asked
regarding what kind of source code license would be appropriate. Kelly
suggested a BSD style license. Kelly also stated that he is looking for
someone to supply him with realistic test models.
Michael noted that the current editorial and clarification changes will be
presented to the IBIS futures group at its next meeting in early February.
Finally, Michael outlined a few technical changes he would like to see the
ICM specification adopt, including allowing multiple types of data within a
single ICM model pair and differential S-parameters. He stressed that these
changes should be considered only after the current draft 1.0 specification
has been passed and adopted.
In the following open discussion Scott McMorrow stated that he has access
to several connector models, and if the specification was solid he would
be willing to convert one of them to ICM format and send it to Kelly.
Models can be sent to Kelly's e-mail at kgreen22@mindspring.com. Stephen
noted that when sending models to Kelly, please indicate if the model can
be released as an example or model template.
A BIRD75 MULTI-LINGUAL EXAMPLE
Lynne Green, Cadence Design Systems
Lynne presented a block diagram of a three transistor receiver with clamp
diode and showed how this receiver would be expressed in a model using
either SPICE or VHDL-AMS. The example also illustrated the BIRD75 syntax
for calling the external SPICE or VHDL-AMS file. Lynne noted that this is
an example and didn't include such items as series diode resistance and
capacitance.
The question was asked if any IBIS keywords besides the ones show could be
placed in between the [External Model]/[End External Model] keywords. Lynne
replied that no, only the keywords shown could be used. However, in response
to another question, Lynne noted that the standard I-V and V-T tables and
other keywords can be included outside the [External Model]/[End External
Model] keyword pair and in a normal [Model].
Several attendees asked what the driving force would be behind creating new
models using the capabilities offered by multi-lingual modeling. Stephen
Peters pointed out that initially multi-lingual modeling will only be used
for the 5% of buffers that can't be modeled any other way. Over time Stephen
expects a library or template of models to develop. Scott McMorrow cautioned
that current IBIS model takes lots of time and multi-lingual modeling
represents another level of effort. He also opined that SPICE option of
the multi-lingual capability will be used more than the AMS capability.
AD HOC DISCUSSION
Tom Dagostino asked for advice on an unusual modeling problem he has been
dealing with. When extracting data for an particular LVT buffer the measured
rising waveform with the load tied to ground was faster than the rising
waveform with the load tied to VCC. This is not usually the case, and will
result in different output waveforms in different simulation tools. Tom
asked if this is a new phenomena that simulation tools need to take into
account or was there a better way to extract the data. There was much
speculation on what physically was going on inside the buffer to cause this,
but no firm conclusions or recommendations were offered.
Raj Raghuram is using IBIS models in power and ground bounce simulations and
his simulations are predicting more power and ground noise than he measures.
Raj suspects that the model is not including enough on-die power to ground
capacitance, and he asked if the expanded C_comp parameters can be used to
include this capacitance. Arpad Muranyi replied that C_comp can be used to
model on-die capacitance, or one could also use the BIRD75 extensions to
create a multi-lingual model. Arpad also pointed out, confirming Bob Ross'
idea, that another way of modeling on-die power and ground capacitance is
to use the [series cap] keyword between two pins. Bob commented that it is
hard to model this capacitance unless the model maker is in direct contact
with the silicon designer.
CONCLUDING ITEMS
Stephen Peters thanked the presenters for great presentations. He noted
that the next teleconference meeting is scheduled for Friday, February 14,
2003. Bob Ross mentioned that the next IBIS Summit meeting will be held at
the DATE conference in Munich, Germany on Friday, March 7, 2003.
============================================================================
NOTES
IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
stephen.peters@intel.com
Senior Hardware Engineer, Intel Corporation
M/S JF4-215
2111 NE 25th Ave.
Hillsboro, OR 97124-5961
VICE CHAIR: Lynne Green (425) 788-0412, Fax: (425) 788-4289
lgreen@cadence.com
Senior Modeling Engineer, Cadence Design Systems
20 120th Ave NE, Suite 103, Bellevue, WA 98005-3016
SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
guy_deburgh@mentor.com
Senior Manager, Mentor Graphics
1369 Del Norte Rd.
Camarillo, CA 93010-8437
SECRETARY ELECT: Randy Wolff (208) 363-1764, Fax: (208) 368-3475
rrwolff@micron.com
Simulation Engineer, Micron Technology, Inc.
8000 S. Federal Way
Mail Stop: 711
Boise, ID 83707-0006
LIBRARIAN: Roy Leventhal (847) 590-9398
roy.leventhal@ieee.org
Consultant, Leventhal Design and Communications
1924 North Burke Drive
Arlington Heights, Illinois 60004
WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504
shuq@cisco.com
Manager, Hardware Engineering, Cisco Systems
170 West Tasman Drive
San Jose, CA 95134-1706
POSTMASTER: John Angulo (425) 497-5077, Fax: (425) 881-1008
John_angulo@mentor.com
Development Engineer, Mentor Graphics
14715 N.E. 95th Street, Suite 200
Redmond, WA 98052
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