Subject: [IBIS] Open forum European Summit minutes (03/07/03)
From: rrwolff (rrwolff@micron.com)
Date: Fri Mar 14 2003 - 09:17:18 PST
DATE: 03/14/03
SUBJECT: March 7, 2003 EIA IBIS Open Forum European Summit Minutes
VOTING MEMBERS AND 2003 PARTICIPANTS LIST:
Ansoft Corporation (Eric Bracken)
Apple Computer Kim Helliwell
Applied Simulation Technology Fred Balistreri
Cadence Design Lynne Green
Cisco Systems Syed Huq, Val Mandruson, Hung Pham
Cypress Semiconductor (Rajesh Manapat)
Hitachi ULSI Systems Kazuyoshi Shoji*
Huawei Technologies (Jiang Xiang Zhong)
IBM (Pravin Patel)
Intel Corporation Stephen Peters, Michael Mirmak,
Arpad Muranyi
LSI Logic Frank Gasparik
Matsushita (Panasonic) Atsuji Ito
Mentor Graphics Bob Ross, Ian Dodd, Guy de Burgh,
John Angulo, Mike Donnelly, Weston Beal
Micron Technology Randy Wolff
Mitsubishi (Pat Hefferan)
Molex Incorporated Gus Panella
Motorola (Rick Kingen)
National Semiconductor Milt Schwartz, Tim Coyle
NEC Electric Corporation (Itsuki Yamada)
North East Systems Associates Edward Sayre
Philips Semiconductor (D.C. Sessions), Stephanie Goedecke*
Quantic EMC (Mike Ventham)
Siemens (& Automotive) AG Eckhard Lenski*, Michael Kindij*,
Burkhard Muller*, Katja Koller*,
Andre Goerisch*, Manfred Maurer*,
Bernard Unger*, Amir Motamedi*,
Hartmut Ibowski*, Gerald Bannert*
Signal Integrity Software (Bob Haller), Barry Katz, Doug Burns
Sigrity Raj Raghuram
SiQual (Rob Hinz)
Texas Instruments Thomas Fisher
Teraspeed Scott McMorrow, Tom Dagostino,
Kevin Simpson
Time Domain Analysis Systems Dima Smolyansky, Steve Corey
Via Technologies (Weber Chuang)
Zuken (& Incases) Michael Schaeder*, Ralf Bruning*,
OTHER PARTICIPANTS IN 2003:
Agilent Technologies Herbert Lage*
Brocade Frank Yuan, Yongrue Yu
Conexant Gary Felker
EADS CCR Alix de la Villeguerin*
EFM Ekkehard Miersch*
EMC Corporation Brian Arsenault
Fraunhofer IZM Ege Engin*
Fujitsu Tadashi Arai
GEIA (Chris Denham)
Independent Kelly Green
Infineon Tech AG Christian Sporrer*
Marvell Semiconductor Itzik Peleg
NetLogic Microsystems Eric Hsu
Plexus Joseph Socha
Politechnico de Torino Igor Stievano*
Sintecs BV Hans Klos*, Bob te Nijenhuis*
Xilinx Susan Wu
In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.
Upcoming Meetings: The bridge numbers for future IBIS teleconferences are
as follows:
Date Bridge Number Reservation # Passcode
March 28, 2003 (916) 356-2663 4 1471937
All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after. When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.
NOTE: "AR" = Action Required.
-------------------------------- MINUTES -----------------------------------
INTRODUCTIONS AND MEETING QUORUM
The European IBIS Summit Meeting was held all day at the ICM conference in
Munich, Germany. About 22 people from 11 companies and institutes attended.
The notes below capture some of the meeting content and discussions. The
meeting presentations and other material are uploaded at:
http://www.eda.org/pub/ibis/summits/mar03/
Ralf Bruening opened the meeting and asked everyone to introduce themselves.
The EDA, user and semiconductor groups were well represented. Ralf thanked
the co-sponsors for the meeting, Mentor Graphics, Siemens, and Zuken for
sharing the meeting expenses. In particular, Ralf thanked Françoise
Lindecker of Mentor, Eckhard Lenski and Manfred Maurer of Siemens, and the
Zuken staff for helping in the meeting logistics, collecting registrations,
and copying presentations.
Ralf then gave a brief overview of the meeting agenda:
9:00 Sign-In/Welcome (R. Buening/Zuken)
- Introduction of Meeting/Objectives/Schedule all
- Participants all
9:40 Basic IBIS Tutorial (E. Lenski, Siemens AG)
10:10 IBIS Version 4.0 Overview - What's New Compared to Version 3.2
(R. Bruening/M. Schaeder, Zuken)
10:35 IBIS Quality Committee Overview (B. Katz/ E. Lenski, Siemens AG)
10:50 IBIS EBD's - What They Are and How They Could/Should be Handled in the
Design Process
(Michael Schaeder, Zuken)
11:25 Quality of IBIS models, IBIS for LVDS (C. Sporrer,Infineon)
12:00 Casual Sandwich Lunch
12:45 IBIS Extension for High Speed Simulation in the Gigahertz Range
(E. Miersch / EFM)
13:00 Three-Pole Modeling (E. Engin, FhG/IZM))
12:25 Radial Based Function Modeling (F. Canavero, Politecnico di Torino)
13:45 Discussion/Question & Answers (all)
14:30 End of Meeting
IBIS BASICS TUTORIAL
Eckhard Lenski, Siemens AG, Germany
Eckhard Lenski started the presentation with an overview of the increased
complexity of IBIS models starting with IBIS 1.1 up to IBIS 4.0. He showed
an example of a current IBIS 3.2 model separated into 4 parts: pin and
package information, different model spec parameters, V-I curves, and V-T
curves. Eckhard presented a table that showed which V-I curves are
referenced to VCC, depending on the model type and technology used. He
continued with examples for a power clamp curve, a pullup curve, and ECL
pullup and pulldown curves. He gave an overview of the parameters used for
ramp and waveforms, their default values, and how to use them properly.
He ended with a summary about different model-types, where each foil
contained the basic IBIS block, the IO-structure and the corresponding
waveforms.
IBIS VERSION 4.0 OVERVIEW - WHATS NEW COMPARED TO VERSION 3.2
Ralf Bruening and Michael Schaeder, Zuken Germany
Ralf Bruening began with information about the IBIS versions of models
obtained from the internet for the designs they analyzed for their
customers. It was about 30% in IBIS 3.2 format, 65% in IBIS 2.1 format, and
still about 5% of the models in IBIS 1.1 format. He gave an overview of the
BIRDS that are now part of IBIS 4.0. The golden waveform shows how the IO
should react at a given test load with spice simulation. He pointed out that
the fall back submodel was introduced due to the lack of trigger functions
available for the bus-hold submodel. He explained that the new receiver
threshold parameters are necessary due to new technologies, including
information about the slew rates at the inputs. He explained that the C_comp
parameter is now split into 4 parts. Then he asked the question that when
there are the 4 reference parameters (instead of voltage range), where is
the C_comp value referenced to. No one in the audience could give him a
quick answer. He also mentioned that the expansion to 1000 points in the
rising/falling waveform tables would further increase the accuracy of IBIS
models. He mentioned that there are future expansions planned (especially
BIRD75) and ended with the statement that IBIS is a living standard that is
driven by the users.
In the followup discussion he pointed out that the golden waveform is not
limited to just a resistive load, but that there are possibilities for a
test load, including transmission lines scenarios. It was noted that,
for example, the C_comp split up into 4 parts will complicate the model
creation and that a black box extraction for the C_comp value will be
difficult.
IBIS QUALITY COMMITTEE OVERVIEW
Barry Katz, Signal Integrity Software (SiSoft), USA, and
Eckhard Lenski, Siemens AG, Germany
Eckhard Lenski began by noting that the goal of the quality committee is to
achieve models with no parser errors or warnings. The focus over the past
year has been the creation of a quality checklist and rating system.
Eckhard defined the quality levels as:
level 0 - passes IBISCHK and includes a few required keywords
level 1 - complete with all needed keywords, pin lists, and data for all
three corners.
level 2a - models have been run through a simulator and correlated to a
transistor level model
level 2b - models have been correlated to bench measurements
level 3 - level 2a and level 2b
The committee is now working on a document that explains the various
checklist items. All attendees said that the quality committee is a very
good approach to getting more accurate models. In the discussion there was
a proposal for a golden buffer, which should be discussed in the quality
committee. Further on, Eckhard pointed out that the results of the checklist
will be part of the IBIS model itself, marked by the comment character "|"
and followed by "IQ" for IBIS Quality.
QUALITY OF IBIS MODELS, IBIS FOR LVDS
Christian Sporrer, Infineon AG, Germany
Dr. Sporrer started with some references to the standards for LVDS and
pointed out that there are a number of publications available to help the
model maker create LVDS-models. He mentioned that it is not possible to
model one output as standalone. So, for the model creation process, the
differential character of LVDS must be taken into account. He explained
that he had created two models, one for CMOS technology and one for bipolar
technology. Then, he compared the models from spice with transistor level
spice simulations using the IBIS model and also with a PCB analysis tool.
For the CMOS model he saw differences. With the IBIS model in spice there
was a shift of the crossing point for the differential output curves from
1.2V up to a voltage of 1.3V. This made the outputs unsymmetrical. Looking
only at the differential signal shows very good correlation. The comparison
of spice and PCB tools showed a big overshoot at the inputs, and it was not
clear where this overshoot came from. For the bipolar LVDS-model, the
appearance of the signal with PCB tools was unsymmetrical. The main problem
was the difference in pulse width symmetry and the dc-shift of the waveform
crossing. He said that it was not clear whether the origin of this problem
came from the IBIS model or the IBIS simulation. One reason may be the model
for the transmission line itself. From the discussion came up the clue that
LVDS is a current driver technology, but the way it is modeled in IBIS is as
a voltage controlled technology. Another idea was to model the LVDS with
four waveforms instead of two as in this example. The last idea was to
create a kind of golden test buffer (similar to the golden waveform) for
the different tools, but it is clear that this would be very problematical
concerning tool revisions, etc. He ended with the statement that he is
looking for more information on how to define/check the quality of a model.
IBIS EBD'S - WHAT THEY ARE AND HOW THEY COULD/SHOULD BE HANDLED IN THE
DESIGN PROCESS
Michael Schaeder, Zuken Germany
Michael Schaeder explained why a description for DIMM modules, etc. is
necessary. He continued with a list of limitations, like coupling between
paths and how to get transmission line parameters for the EBD. In the next
slides he showed different examples of EBD paths, and then he switched over
to some common problems like unsolved external references, unclear order of
lumped R, L, and C elements (with Len=0), and the confusion among new users
with the arbitrary unit length. He then showed two ways of using an EBD file
in PCB simulations. The first was to read in the .ebd/.ibs files at
simulation time, which means that the design and the EBD data must fit
together. The second way was to convert the EBD file into the simulation
environment. That way the EBD behaves as normal parts/transmission lines on
the board itself. He ended with some hints about describing multi-level dies
in an EBD format and a question of when the coupling between lines might
be possible.
LUNCH
The group recessed for a brief working lunch.
IBIS Extension for High Speed Simulation in the Gigahertz Range
Dr. E. Miersch, EMC / SIGRITY, Inc.
Dr. Miersch made a short ad-hoc-presentation. He showed that simulation with
IBIS models having a rise/fall time of about 100ps is possible, but the key
to doing this is both good models of the IO buffer and the package. The
package model for the ASIC shown was created for a 4-layer BGA. He showed
good agreements between measurement and simulation.
THREE-CONDUCTOR MODELING OF POWER/GROUND NOISE
Ege Engin, Fraunhofer Institute Reliability and Microintegration, Germany
Ege Engin described the reasons why there is a need to enhance modeling of
Power/Ground noise in chip packages. He explained the differences between
the 2-conductor model and the new 3-conductor model. He showed an example of
a 3-conductor spice model, which contains an ibis output driver model and a
3-conductor interconnect model. The ideal power distribution system of the
2-conductor model will be replaced by one model for the power plane and
one model for the ground plane. Doing this, all current return paths can be
considered. The 3-conductor model shows that for H-L transitions the current
return path is mostly in the power line and for L-H transitions it is mostly
in the ground line. Assuming that the ratio of signal lines to power lines
plus ground lines must be equal, he showed that furthermore the ratio of
power lines to gnd line must also be equal. In his conclusions he remarked
that an extended IBIS model that includes coupling between the package pins
is necessary for further improvements, and also an enhanced IBIS model of
the driver that contains data for non-ideal power supply conditions would be
welcome. In the discussion he pointed out that the model is at moment
frequency limited, but this can also be improved.
M(PI)LOG, MACROMODELING VIA PARAMETRIC IDENTIFICATION OF LOGIC
F.G. Canevero, I.A. Maio, I.S. Stievano, Politecnico di Torino, Italy
Igor Stievano showed a new approach for behavioral models in the case that
spice models are not available and IBIS models are not adequate enough. The
new model will also contain information about temperature and VCC
fluctuations. It is a mathematical expression that reproduces the electrical
behavior of the IO stage. The reaction of the IO stage to a convenient
stimulation is used to build a model by creating a set of non-linear
Gaussian radial basis functions. This solution conforms with the BIRD75.8
multilingual modeling. The created model of a tri-state output shows good
correlation with spice simulations, and the computation rate is about 20 to
100 times faster. A tool creates the models, and it takes about 5 minutes of
CPU-time. He observed no load dependency of his model in the examined range
of 20-100 Ohm test loads. The model also contains voltage-variations in the
range of +/- 15%. In the discussion he pointed out that the next step would
be to use this approach to model a differential output. He also mentioned
that the M(PI)LOG model could be included like a normal spice subcircuit.
CONCLUDING REMARKS
Ralf Bruening thanked the participants for attending and the presenters for
providing a fine set of presentations. Ralf also thanked the sponsors for
keeping the European IBIS Summit Meeting active.
Ralf mentioned that there was much interaction during the breaks and that it
was a very successful meeting.
NEXT MEETING
The next teleconference meeting is scheduled for March 28, 2003 from 8:00 AM
to 10:00 AM Pacific time. A vote on BIRD74.2 and BIRD79 is scheduled.
============================================================================
NOTES
IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
stephen.peters@intel.com
Senior Hardware Engineer, Intel Corporation
M/S JF4-215
2111 NE 25th Ave.
Hillsboro, OR 97124-5961
VICE CHAIR: Lynne Green (425) 788-0412, Fax: (425) 788-4289
lgreen@cadence.com
Senior Modeling Engineer, Cadence Design Systems
20 120th Ave NE, Suite 103, Bellevue, WA 98005-3016
SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475
rrwolff@micron.com
Simulation Engineer, Micron Technology, Inc.
8000 S. Federal Way
Mail Stop: 711
Boise, ID 83707-0006
LIBRARIAN: Roy Leventhal (847) 590-9398
roy.leventhal@ieee.org
Consultant, Leventhal Design and Communications
1924 North Burke Drive
Arlington Heights, Illinois 60004
WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504
shuq@cisco.com
Manager, Hardware Engineering, Cisco Systems
170 West Tasman Drive
San Jose, CA 95134-1706
POSTMASTER: John Angulo (425) 497-5077, Fax: (425) 881-1008
John_angulo@mentor.com
Development Engineer, Mentor Graphics
14715 N.E. 95th Street, Suite 200
Redmond, WA 98052
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