Subject: RE: [IBIS] about Vref
From: Muranyi, Arpad (arpad.muranyi@intel.com)
Date: Mon Aug 25 2003 - 09:16:57 PDT
Wil,
Those are two different things. The ***ref parameters tell the
simulator
how the reference driver should be loaded. At that load, at Vmeas is
where
Tco is valid. The ***fixture parameters tell the simulator how the
buffer
was loaded for the waveform generated. This is useful for calculating
the currents during the high to low / low to high transitions.
Arpad Muranyi
Intel Corporation
========================================================================
====
-----Original Message-----
From: Wil Ngan [mailto:wngan@idt.com]
Sent: Thursday, August 21, 2003 3:37 PM
To: tom@teraspeed.com; ibis@eda.org
Subject: RE: [IBIS] about Vref
Tom,
I have a question regarding one of your replies I found in the
IBIS archives. The V,R,C refs, do these values
have any correspondence to the V,R,C fixture parameters
listed in the [Rising/Falling Waveforms]? Also, are these
V,R,C refs usually listed on datasheets?
Wil
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Subject: RE: [IBIS] about Vref
From: Tom Dagostino ( tom@teraspeed.com
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Date: Tue Apr 29 2003 - 08:52:02 PDT
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_____
Vref is part of the Timing Test Load. This is the load that the
manufacturer guarantees the timing of the component. The Timing Test
Load
is made up of three parts, Vref, Rref and Cref. Rref is a resistor tied
between the output of the device and the reference voltage Vref. Cref is
connected to the output and to ground. These values are selected by the
manufacturer or are specified in some cases by the standard interface
the
logic drives.
Vmeas is the voltage value that timing is measured to. It is also part
of
the timing specification.
Usually when you get the warning listed in your note either the driver
is
too weak to drive the Timing Test Load or the wrong Timing Test Load was
included. I've also seen Timing Test Loads for open sink drivers (open
drain/open collector) that have Vref = 0. This will not work at all. An
open sink needs a Vref usually at Vdd.
Tom Dagostino
Teraspeed Consulting Group LLC Teraspeed Consulting Group LLC
2926 SE Yamhill St. Device Modeling Division
Portland, OR 97214 13610 SW Harness Lane
Beaverton, OR 97008
http://www.teraspeed.com 503-430-1065
tom@teraspeed.com
<mailto:tom@teraspeed.com?subject=RE:%20%5BIBIS%5D%20about%20Vref&replyt
o=005101c30e67$48819ca0$6a01a8c0@teraspeedmodeling.com>
-----Original Message-----
From: owner-ibis@server.eda.org
<mailto:owner-ibis@server.eda.org?subject=RE:%20%5BIBIS%5D%20about%20Vre
f&replyto=005101c30e67$48819ca0$6a01a8c0@teraspeedmodeling.com>
[mailto: owner-ibis@server.eda.org
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f&replyto=005101c30e67$48819ca0$6a01a8c0@teraspeedmodeling.com> ]On
Behalf Of Lior Aviv
Sent: Tuesday, April 29, 2003 7:44 AM
To: ibis@server.eda.org
<mailto:ibis@server.eda.org?subject=RE:%20%5BIBIS%5D%20about%20Vref&repl
yto=005101c30e67$48819ca0$6a01a8c0@teraspeedmodeling.com> ;
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Subject: [IBIS] about Vref
Hello,
I have IO that works with 3.3v +-10%.
The output resistance is 50 Ohm.
My questions are regarding the Vref parameter -
1. Who should set it and how?
2. While running the ibis checker3, I have noticed that there is a
relation
between the Vref and the Vmeas but could not understand what does
the
checker exactly check with these parameters.
The warnings I get are not so clear -
" Model 'xxx': MIN VI curves cannot drive through Vmeas=1.5V
given load Rref=50 Ohms to Vref=zzzV ".
Thanks,
Lior Aviv,
MSIL.
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