[IBIS] Basic questions about IBIS

Hi, experts,

    I am a hand-held device hardward engineer who just study IBIS simulation for serveral months.
    I have some basic questions:

1. Is it possible to simulate setup/hold time using IBIS model?
    I know that we can obtain the delay difference between "test load" and "trace", but I don't know whether it is possible to ask chip vendors to provide the "gate delay + test load" of each signal.

2. What item is the main purpose of signal integrity simulation works? Overshoot, ringback, transition time, or crosstalk?

3. Is measurement-based IBIS model more accurate that SPICE simulation-based IBIS model?
    One of our chip vendor said it, and we do obtain more accurate results from measurement-based IBIS model. However, they said that it takes 3-4 months to generate a measurement-based IBIS model, so they are not willing to generate the IBIS model of the other I/O buffers on the same device for us.
    Is it possible to generate an accurate enough IBIS model in a short time?

4. When we want to generate a measurement-based IBIS model How can we select the max, min, typ buffer strength chip?

5. In IBIS, the "max" curves are measured / simulated under the condition "maximum buffer strength + lowest temperature + largest voltage"
         and the "min" curves are measured / simulated under the condition "minimum buffer strength + highest temperature + smallest voltage".
    I think it is not sufficient to simulate the ringback: as I know the ringing caused by maximum buffer strength is much larger the minimum buffer strength, but "smallest voltage - VIH" is smaller than "largest voltage - VIH", we cannot make sure whether the ringback margin is sufficient even if the simulation results of min and max passed. (Because the smallest ringback margin should be under the condition "maximum buffer strength + lowest temperature + smallest voltage")

6. Chip vendors usually set the largest and smallest voltage according to their maximum tolerance (for example 20%), however, the voltage error rate of our regulator is usually not so large. So the worst cases in IBIS model are not the same with the worst cases in our PCBA. Furthermore, sometimes the typical voltage we use is not the same with the original. I would like to know whether there is a method to generate the IBIS model we need.

     Any help will be apreciated, Thanks in Advance.

Best regards
Andrew

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Received on Wed Dec 29 01:52:00 2004