RE: [IBIS] Comments on BIRD 95.2.

Hello Bob

Thanks for your replies. It is still not clear. What is the connection
between BIRD95 and [Pin Mapping]. As far as I understand BIRD95 describe
the current profile of the buffer when switching while [Pin Mapping]
describe the connectivity of the buffers to each power rail and also
include package parasitic.

Please elaborate. 


--
Regards
 
Itzik Peleg
Board Technology Group
 
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-----Original Message-----
From: Bob Ross [mailto:bob@teraspeed.com] 
Sent: Monday, March 14, 2005 3:34 PM
To: Itzik Peleg
Cc: ibis@eda.org
Subject: Re: [IBIS] Comments on BIRD 95.2.

Hello Itzik:

Thank you for your comments.  We agree and will add the time
correlation information to the next revision.

Also, thank you for indicating that the two paragraphs were not
clear.  We will also have to fix that.

To answer briefly your questions:

(1) The [Pin Mapping] keyword is specifically mentioned as
the assumed method to tell the tool which pins are used for
the power and ground connections for each buffer.

(2) The second statement is more of a cautionary note to
describe what the [Composite Current] was NOT designed to
consider.  The various [Submodel]s document the approximate
behavior of some additional elements that could exist
in the I/O buffer architecture.  These elements are
"triggered" by voltage crossings in the actual circuit.
This triggering is not correlated with any [Composite Current]
contributions that might exist from test *_fixture
loads.

To a lessor extent, the same applies to [Driver Schedule]
models which get triggered by time delays.  For some
keyword structural reasons which I do not want to describe
in this response, the additional currents for each submodel
may not accurately be allocated to the major power rail.

So a cautionary note is needed to state conditions where
the [Composite Current] keyword may not apply.

Bob

Itzik Peleg wrote:
> Hello All
> 
>  
> 
> I have one comment and one question regarding BIRD95.2:
> 
>  
> 
> Comment:
> 
> Since V(t) and I(t) need to be time correlated I think that there
should 
> be an explicit remark regarding that. (I had mention that in earlier 
> teleconference).
> 
>  
> 
> Question:
> 
>  
> 
> This is a quote from BIRD95.2:
> 
>  
> 
> |              The [Pin Mapping] keyword is used to docuemnt the
voltage 
> rails
> 
> |              of several buffers are combined.  This combination 
> includes the
> 
> |              effective impedances describe for each buffer
> 
> |
> 
> |              The [Composite Current] keyword is not designed to
accurately
> 
> |              document the effects of controlled switching buffers
such as
> 
> |              those defined with [Submodel] or [Driver Schedule]
keywords.
> 
>  
> 
> Please elaborate on these 2 remarks. I didn't understand it.
> 
>  
> 
> --
> 
> Regards
> 
>  
> 
> Itzik Peleg
> 
> Board Technology Group
> 
>  
> 
> ***********************************************************
> 
> Please Note: email address change to: itzikpe@marvell.com
<mailto:itzikpe@marvell.com>
> 
> ***********************************************************
> 
>  
> 
> Marvell Semiconductor Israel Ltd
> 
> 6 Hamada Street 
> 
> 
> 
> Mordot HaCarmel Industrial Park
> 
> 
> 
> Yokneam 20692, ISRAEL
> 
> Email - itzikpe@marvell.com <mailto:itzikpe@marvell.com>
> 
> Tel   - +972 4  9091192
> 
> Cell  - +972 54 4452482
> 
> Fax   - +972 4  9091501
> 
> WWW Page: http://www.marvell.com <BLOCKED::http://www.marvell.com>
> 
>
========================================================================
> 
> This message may contain confidential, proprietary or legally
privileged
> 
> information. The information is intended only for the use of the
> 
> individual or entity named above. If the reader of this message is not
> 
> the intended recipient, you are hereby notified that any
dissemination,
> 
> distribution or copying of this communication is strictly prohibited.
> 
> If you have received this communication in error, please notify us
> 
> immediately by telephone, or by e-mail and delete the message from
> 
> your computer.
> 
>  
> 
> Thank you!
> 
>
========================================================================
> 
>  
> 

-- 
Bob Ross
Teraspeed Consulting Group LLC     Teraspeed Labs
121 North River Drive              13610 SW Harness Lane
Narragansett, RI 02882             Beaverton, OR 97008
401-284-1827                       503-430-1065
http://www.teraspeed.com           503-246-8048 Direct
bob@teraspeed.com

Teraspeed is a registered service mark of Teraspeed Consulting Group LLC



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