[IBIS] BIRD95.5 and the next steps

Hi everyone,

Power Integrity Analysis encompasses the die(core)+io+pkg+pcb
environment with lots of challenges to solve at each stage. When we
started with BIRD95.0, we also envisioned the interactions needed
between the Core and I/O using the ICEM modeling scheme. We also relied
on ICM to define many of the interconnects needed for a total Power
Integrity Analysis. While these are still to be solved, the problem is
complex no doubt.

So, we simplified by breaking the issues into multiple pieces. BIRD95.5
with it's I/T tables and [Composite current] keyword (only 2 new keyword
added), solves the SSN simulation. That is all this current proposal is
meant to do.

With Arpad's BIRD98/97.2, Gate Modulation Effects are handled.

We also welcome other BIRDs/Proposals to solve the remainder of the
pieces to address the total Power Integrity Analysis.

In the IBIS Summit meeting, we showed BIRD95.5 working on a multi-buffer
SSN simulation scenario to prove once again that this proposal is
effective. 
http://www.eda.org/pub/ibis/summits/jun05/yang.pdf

We encourage you to address the DC grid issues Cadence had brought up at
the DAC Summit etc or attempt to address the other PI issues out there.

As of Apr29th, BIRD95.5 has not gone thru any further changes. We are
open to hearing any technical issues you may have that is related to
BIRD95.5 and it's specific proposal.
http://www.vhdl.org/pub/ibis/birds/bird95.5.txt

With your support, we look forward to taking the next step in solving
Power Integrity Analysis using IBIS.

Best Regards,
Syed
-- 
Cisco Systems, Inc
Vice-Chair EIA IBIS Forum
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