[IBIS] To capture the delay variation with change in IO voltage

Hi Gurus,

I have generated an IBIS model using rated IO voltage(1.5V) and
simulated it at the same IO voltage(1.5V); the matching between 
hspice vs IBIS is very good (1st waveform in attached *.pdf). When I
simulated the same IBIS model with reduced IO voltage (1.1v), 
the matching is poor (2nd waveform) between IBIS and hspice models. IBIS
model is not able to capture the delay variation with supply voltage
variation.

Next, I have re-generated the IBIS model with reduced IO voltage(1.1V)
and the simulation at this voltage(1.1V) gives good matching 
(3rd waveform) between IBIS and hspice models.

Means IBIS model can not be used to see the variation in delay with the
ripples on IO voltage? Is it known limitation?

Are there any techniques/methods exist to build an IBIS model, which can
be used to simulate at an IO
voltage lesser/greater than the voltage at which it is build?

Here, I am attaching a PDF of the waveforms I observed.

Could some one help me in clarifying the above queries?

Thanks in advance.

Best Regards,
Venu

 <<ibis_hspice_delay.pdf>> 



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