[IBIS] IBIS modelling for internal parallel terminations

Hello all,

How do we model a buffer with internal parallel terminations where in the
termination is between pad and vss and also between pad and supply.
How to generate final POWER and GND clamps that need to be reported in 
IBIS file.
(to avoid double counting)

cookbook does not include this scenario.

Is this difficult to model or do we have ways to handle this.

Regards
vinayak
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