Ray, First, I'm happy to see you using the IBIS Quality Specification. If you wish I can add you to the IQ reflector on Freelists. An IBIS Quality task force working review copy of the IBIS Quality Specification adds a footnote to IQ 4.4.2: ibischk v4.0.2 detects this, but [IBIS ver] must be 4 So the IQ 4.4.2 check as described is the one already performed by ibischk. According to the note ibischk currently performs the check this way only in IBIS 4.x files. But looking at the ibischk code I think it will check combined curves for all files, not just 4.x and above. So the note may be partly mistaken. The net result is that you only need run ibischk to check this. An example of the warning: WARNING - Model testbuf: The [Falling Waveform] with [R_fixture]=50 Ohms and [V_fixture_min]=3V has MIN column DC endpoints of 2.00V and 3.00v, but an equivalent load applied to the model's I-V tables yields different voltages ( 1.93V and 3.00V), a difference of 6.50% and 0.00%, respectively. Mike ________________________________ From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Ray Anderson Sent: Monday, September 11, 2006 3:20 PM To: ibis@eda-stds.org; ibis-users@eda.org Cc: Ray Anderson Subject: [IBIS] Question on IBIS Quality Spec Interpretation (section 4.4.2) One of our development groups is currently reviewing one of our new IBIS models for LEVEL 0 compliance prior to initial issue to customers. A question has come up regarding the interpretation of section 4.4.2 in the iq_specification.txt document (IBIS QUALITY SPECIFICATION - Revision 1.0). While the text of the document defines the intent very precisely, can someone please provide an interpretation of what really needs to be checked? Initially the group thought it was as simple as verifying that the voltages at the endoints of the V-T table were within 2% of the endpoint voltages in the I-V tables, but after re-reading section 4.4.2 we are not convinced that is a correct interpretation. 4.4.2 {LEVEL 0} V-T table endpoints consistent with I-V tables The voltage associated with the intersection of the V_fixture, R_fixture, and R_dut (if present) load line with the respective combined high/low DC I-V characteristic should be within 2% of the V-T table DC endpoints based on the V-T table DC range. The combined High State DC I-V characteristic is defined as the sum of the [Power Clamp], [GND Clamp], and [Pullup] I-V tables (ground relative). Similarly, the combined Low State DC I-V characteristic is defined as the sum of the [Power Clamp], [GND clamp], and [Pulldown] I-V tables (ground relative). -Ray Anderson Raymond Anderson Senior Signal Integrity Staff Engineer Product Technology Department Advanced Package R&D Xilinx Inc. -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis <optional e-mail address, if different> | subscribe ibis-users <optional e-mail address, if different> | unsubscribe ibis <optional e-mail address, if different> | unsubscribe ibis-users <optional e-mail address, if different> | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993Received on Tue Sep 12 16:53:44 2006
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