[IBIS] RE: VOL, VOH, Vmeas, VIL, VIH

Hi Beatrice,

Here are some answers for you.

1) Vmeas is used to measure system timing by certain tools. VIL and VIH are the receive thresholds guaranteed across PVT by the silicon manufacturer. Vol and Voh are not required and are often omitted from IBIS models, because it is well understood what occurs if logic families are mixed. If designing with the same logic family, this is not a problem. But your question seems to indicate this design involves mixing logic families.... if so, see the link below.

2) Correction: LVTTL Standard thresholds are VIL = 0.8V and VIH= 2.0V. Not "about 1.7V." The receive waveform must be monotonic within this range or there will be production fall-out and/or reliability problems.

There are two portions to the problem you're asking.

1) The real problem: The simulation is showing non-monotonic signals at the receiver, which means the system is not correctly terminated. This causes ISI for some actual receivers. The "dogleg" you describe is due to reflection from an impedance mismatch (EM boundary condition). So this system either needs series termination(one receiver on the bus), or active termination (for multiple receivers). CMOS output buffers commonly have a characteristic impedance of 18-34 ohms. Example of series termination: to match a PCB trace impedance of 60 ohms, try inserting a resistor between 22-33 ohms within 1" of the transmitter. I recommend "High Speed Digital Design"(Howard Johnson Ph.D.) for further details on bus termination.

2) An "engineer with grey hair" said you can ignore VIL and VIH: Someone gave you incorrect information based on lab tinkering rather than Electrical Engineering and Physics. If the transition is non-monotonic between VIL and VIH, the system is not guaranteed to work across PVT. "Not guaranteed" means it sometimes works! Now, it is true that actual gates of each receiver have tighter thresholds: this is why a non-monotonic signal may "work in the lab." However at volume production, the present system *will* result in something like 10k unit fallout per 1M units (engineers work on weekends when product yield is that far below Six Sigma). The reason for the range between VIL and VIH for a logic family is to accommodate three effects on the actual charge required to bias an actual gate: silicon process skew, system voltage, and temperature. Thus, for guaranteed operation across PVT, the receiver waveform must be monotonic between VIL and VIH for slow, typical, and fast transmit models. BTW, the reason for the gap between VSS and VIL, VCC and VIH is to accommodate noise and voltage variation in a digital system.

Here is a TI whitepaper describing level translators and logic family compatibility when mixing LVCMOS and LVTTL for different system voltages:
http://www.frbb.utn.edu.ar/electronica/3-tercero/td1/notas-aplic/Voltage%20Translation%205V%20%203,3V%20%202,5V%20%201,8v%20scya006.pdf

Regards,
-Graham Kus
Sr. HW Dev Engineer
Certified SI Engineer

From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of AZANOWSKY Beatrice
Sent: Thursday, July 07, 2011 6:47 AM
To: ibis@eda.org
Subject: [IBIS] VOL, VOH, Vmeas, VIL, VIH

Dear Members,

 Is any one is able to answer at the 2 questions below please?

1) It seems that the IBIS models do not generally use the VOL and VOH. It is only the Vmeas or the Vref that is used. So, if there is Vmeas only that is displayed by the IBIS model and not VOL and VOH, what about the logic states supplied by the driver? Could we say that the level is HIGH if the signal is above Vmeas (and not above VOH) and the level is LOW if the signal is below Vmeas (and not below VOL)?

2) For a LVTTL 3.3V standard, VIL is about 0.8V and VIH is about 1.7V at the receiver. OK.

But, does the receiver strictly use these thresholds to switch its states or does it use others thresholds included in the (VIH(1.7V)-VIL(0.8V)) zone (1V for example instead of 0.8V and 1.4V for example instead of 1,7V)?

Because we have simulations results where VIL (0.8V) and VIH (1.7V) are crossed 2 times. Some people say that it is not a serious problem because in fact the thresholds of the receiver are not at 0.8V but above 0.8V, between 0.8V and 1.7V, and not at 1.7V but below 1.7V, between 1.7V and 0.8V.

Is this right please? Then, could we know what are the thresholds really used by the receiver?

Thank in advance for your help.

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