Hello Walter,
I am missing Multi-Chip-Modules. You can have some dies in one package
which are wired via a substrate or via multiple bonds. Some of this inter
die connection have also connection to the package bumps. I am not
sure if this is considered in your list (1 on-die model instance).
Christian.
On 07/20/12 22:27, Walter Katz wrote:
>
> All,
>
>
>
> Rather than discussing the possible IBIS solutions for package models,
> I would like to describe the physics of the problem, and then ask some
> questions of what part of the physics need to be implemented.
>
>
>
> I would like to frame these questions with an example:
>
>
>
> Package
>
> 150 VDD Pins
>
> 150 VSS Pins
>
> 100 Single Ended Channel Pins
>
> Die Bump Pads
>
> 200 VDD Bump Pads
>
> 200 VSS Bump Pads
>
> 100 Single Ended Channel Bump Pads
>
> Die Buffer Pads
>
> 100 VDD Buffer Pads
>
> 100 VSS Buffer Pads
>
> 100 Single Ended Channel Buffer Pads
>
>
>
> Complete Package Model (describes the full physics of the package
> interconnect)
>
> 150 VDD Pins
>
> 150 VSS Pins
>
> 100 Single Ended Channel Pins
>
> 200 VDD Bump Pads
>
> 200 VSS Bump Pads
>
> 100 Single Ended Channel Bump Pads
>
> 900 total ports
>
>
>
> Complete On-Die Model (describes the full physics of the die interconnect)
>
> 200 VDD Bump Pads
>
> 200 VSS Bump Pads
>
> 100 Single Ended Channel Bump Pads
>
> 100 VDD Buffer Pads
>
> 100 VSS Buffer Pads
>
> 100 Single Ended Channel Buffer Pads
>
>
>
> A Full Simulation will consist of
>
> Board and all of the stuff on the Board
>
> 1 Package model instance
>
> 1 on-die model instance
>
> 100 IBIS buffers
>
>
>
> Connections that need to be rectified
>
> 400 connections between Board and Package Model
>
> 500 connections between Package Model and On-Die Model
>
> 300 connections between On-Die Model and 100 Buffer Models
>
>
>
> Questions to IC Vendors:
>
> Is this setup is a completer representation of the problem?
>
> Is it practical to produce the Package Model and On-Die Model in this
> level of detail?
>
> Do you want/need to use a subset of the on-die VDD and VSS Bump Pads
> in your On-Die Model?
>
> Do you want to be able to represent the VDD and VSS Bump Pads as two
> nodes?
>
> Do you already include the interconnect between the Channel Bump Pads
> and Channel Buffer Pads in your Buffer Model?
>
> Do you need interconnect between VDD and VSS Bump Pads and VDD and VSS
> Buffer Pads, or is it sufficient to "tie" each VDD and VSS Buffer Pad
> to specific VDD and VSS Bump Pads.
>
> Do you want to be able to distribute Package and On-Die Models for
> slices (subsets) of the 100 Channels?
>
> Do you want to be able to distribute multiple Package and On-Die
> Models with different combinations of the choices above?
>
>
>
> Walter
>
>
>
-- Infineon Technologies AG Vorsitzender des Aufsichtsrats: Wolfgang Mayrhuber Vorstand: Peter Bauer (Vorsitzender), Dominik Asam, Arunjai Mittal, Dr. Reinhard Ploss Sitz der Gesellschaft: Neubiberg Registergericht: München, HRB 126492
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