Re: [IBIS] Overclocking effect with composite current

brad

since power aware models require modeling of the device physics, the
redistribution layer, and the package, it seems to me that a comprehensive
physical model correlation effort is necessary to show that you actually
can show modeling correlation to physical measurements.  If your modeling
is correct, there is no reason why very excellent waveform overlay cannot
be accomplished, especially in the presence of power system impairments.
 to do otherwise would be design malpractice, as designers will use these
models and simulations for design sign-off.

you have reached an important milestone insofar as being able to model the
overclocked buffer with all power impairments.  Now go to the next step to
show that your approach matches physical measurements.   If it does, you
have an incredible case to make.  If not, it would provide interesting
information about weaknesses in the methods, or areas that require
additional modeling support.  Ether way Cadence and the ibis cmmunity win




On Mon, Feb 3, 2014 at 4:58 PM, Bradley Brim <bradb@cadence.com> wrote:

> Hi Scott,
>
>
>
> We began to discuss this topic last Friday afternoon at the IBIS Summit in
> Santa Clara ...
>
> I understand your points now and then as:
>
>     (1) Even a transistor-level model may not represent all the relevant
> behavior of some buffers
>
>     (2) Converting a transistor-level model to an IBIS model does not
> address (1)
>
>     (3) To address (1) a more complex nonlinear transistor-level model is
> likely required
>
> Completely agree with all these points.  Your points are not specific to
> the contribution of the paper cited by Rinsha originally presented in Japan
> or the follow-up paper presented last Friday in Santa Clara.
>
>
>
> We believe it is highly interesting and much more than an academic
> exercise to enable the application of IBIS models instead of
> transistor-level models. Why? Because for analyses such as SSO where
> multiple buffers are applied transient circuit simulation times may be
> literally days when transistor-level models are applied versus minutes when
> IBIS buffers are applied. Memory consumption is also dramatically reduced.
> For specific example please refer to Romi Mayder's paper from DesignCon
> 2013: *"Simulating Simultaneous Switching Noise with IBIS v5.0 Models"*.
> That paper demonstrates the successful application of BIRDs 95 and 98 for
> power-aware IBIS models with quantitative comparisons. The paper cited by
> Rinsha and the similar paper in last Friday's IBIS Summit discuss an
> extension to over-clocking for such power-aware models.
>
>
>
> Correlation to physical measurements would help judge the quality of
> present transistor-level models and guide the development of more complex
> nonlinear transistor-level models. However, the efforts of enabling more
> efficient (w.r.t both time and memory) simulations with IBIS models should
> be judged on correlation between existing transistor-level models and the
> IBIS macromodels applied in their stead. One could envision producing
> power-aware IBIS models directly from measurements, but as your colleague
> Tom Dagostino pointed out last Friday in the IBIS Summit, the required PDN
> current measurements are extremely difficult (if not impossible) to perform
> with the required accuracy. The correlation with which you seem to be
> concerned is less the added detail of overclocking and more one of the core
> IBIS macromodel itself.
>
>
>
> I don't recall the effects you cited as specific concern last Friday but
> another common concern is that pre-driver currents may be from a different
> power rail than for the analog portion of the buffer. This is not supported
> by the IBIS topology with its present single-rail power.
>
>
>
> Suggest you document your specific concerns with transistor-level and IBIS
> macromodel representation for consideration by IBIS-ATM.
>
>
>
> Best regards,
>
> -Brad
>
>
>
> *From:* owner-ibis@eda.org [mailto:owner-ibis@eda.org] *On Behalf Of *Scott
> McMorrow
> *Sent:* Monday, February 03, 2014 12:50 PM
>
> *To:* Joy Li
> *Cc:* Rinsha Reghunath; ibis@eda.org; ibis-users@eda.org
> *Subject:* Re: [IBIS] Overclocking effect with composite current
>
>
>
> joy
>
>
>
> we at Teraspeed would like to see comparisons between physical
> measurements and simulation that validate your proposed approach. Without
> this, your approach is an interesting academic exercise in translating from
> one approximate modeling format (Spice) to another approximate modeling
> format (Cadence-IBIS-Spice).  You may be solving a problem, but not "the
> problem."  I recognize that "the problem" may not be solved without
> non-linear modeling.
>
>
>
> regards,
>
>
>
> Scott
>
>
>
>
>
> On Mon, Feb 3, 2014 at 2:45 PM, Joy Li <joyli@cadence.com> wrote:
>
> Hi Rinsha,
>
> At this time, there is no further documentation available publicly.
>
> To enable the industry to consolidate on a single approach, we may at some
> time in the future disclose more details concerning our approach to the
> IBIS committee for consideration as part of the standard or best practices
> documentation.
>
> Joy Li
> Cadence
>
> *From:* owner-ibis@eda.org [mailto:owner-ibis@eda.org] *On Behalf Of *Rinsha
> Reghunath
> *Sent:* Monday, February 03, 2014 9:29 AM
> *To:* ibis@eda.org; ibis-users@eda.org
> *Subject:* [IBIS] Overclocking effect with composite current
>
> Hello,
>
> The following paper discusses about the solution for overclocking with
> composite current: http://www.eda.org/ibis/summits/nov13c/sun.pdf
>
> Is there any other documentation further explaining this technique or
> could someone please give more insight on this?
>
> Thanks,
> Rinsha
>
>
>



-- 

Scott McMorrow
Teraspeed Consulting Group LLC
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Falmouth, ME 04105

(401) 284-1827 Business

http://www.teraspeed.com

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