All: Attached is the Agenda for a full meeting with nine presentations. We look forward to seeing you in Yokohama. Registration information is at the end. Bob Ross Teraspeed Labs Yukio Masuko Cadence Design Systems ------------------------------------------------------------------ A S I A N I B I S S U M M I T I N F O R M A T I O N Time/Date: Thursday, November 20, 2014, 12:30 to 16:30 Meeting starts at 13:00 Location: Pacifico Yokohama Conference Center 1-1-1, Minato Mirai, Nishi-ku Yokohama, JAPAN http://www.pacifico.co.jp/english/index.html Room: 503 Organizational Sponsors: Japan Electronics and Information Technology Industries Association (JEITA) IBIS Open Forum Sponsors: ANSYS Cadence Design Systems Cybernet Systems Mentor Graphics Corporation MoDeCH Zuken ------------------------------------------------------------------ I B I S S U M M I T M E E T I N G A G E N D A 12:30 SIGN IN 13:00 Meeting Welcome Shogo FUJIMORI (Fujitsu Advanced Technology, Chair JEITA IBIS Promotion WG) Lance WANG (IO Methodology, Vice Chair IBIS Open Forum) 13:10 Activities and Direction of IBIS Michael MIRMAK (Intel Corporation, USA) 13:30 Introduction of IBIS Promotion Working Group Shogo FUJIMORI (Fujitsu Advanced Technology, Japan) 13:45 Inconsistency of EBD (Electrical Board Description) Specification in DDR3 DIMM Shogo FUJIMORI (Fujitsu Advanced Technology, Japan) 14:05 IBIS Package Model (Past, Present, What's Next) Shinichi MAEDA (KEI Systems, Japan) 14:25 Differential Buffer Using IBIS Models for PDN Simulations Lance WANG (IO Methodology, USA) 14:45 BREAK 15:00 True Differential IBIS Model for SerDes Analog Buffer Shivani SHARMA, Tushar MALIK, and Taranjit KUKAL (Cadence Design Systems, India) 15:20 IBIS AMI Validation Zilwan MAHMOD and Anders EKHOLM (Ericsson, Sweden) 15:40 IBIS Model Engineering Application Possibility Kazuhiko KUSUNOKI (Wadow, Japan) 16:00 Introduction of P2401 LSI-Package-Board Standard Format Yoshinori FUKUBA (Toshiba Semiconductor & Storage, Japan) 16:20 CONCLUDING ITEMS 16:30 END OF MEETING ---------------------------------------------------------------- To Register by November 17, 2014: Name: E-mail address: Company: Top-level Web Link: Country: Send to BOTH: Bob ROSS, Teraspeed Labs bob@teraspeedlabs.com Yukio MASUKO, Cadence Design Systems masuko@cadence.com -- Bob Ross Teraspeed Labs http://www.teraspeedlabs.com bob@teraspeedlabs.com Direct: 503-246-8048 Office: 971-279-5325 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993Received on Mon Nov 10 18:51:45 2014
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