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A Minutes listing is available on a separate page
| Title | Formats | Authors | Organization | Date |
|---|---|---|---|---|
| Quiet Line Experiments (BIRD98) | Arpad Muranyi | Intel Corporation | May 31 2006 | |
| IBIS 5.0 Proposal | .ppt | Michael Mirmak | Intel Corporation | May 24 2006 |
| [Submodel] Name Limit Extension | .txt | Michael Mirmak | Intel Corporation | May 04 2006 |
| A Proposal Regarding Model Encryption | .ppt | Michael Mirmak | Intel Corporation | Apr 19 2006 |
| Draft BIRD104, Rev. 2 | .txt | Randy Wolff | Micron Technologies | Apr 12 2006 |
| Draft BIRD104 | .txt | Randy Wolff | Micron Technologies | Mar 29 2006 |
| ICM and IBIS Proposal - Simple Link | .ppt | Michael Mirmak | Intel Corporation | Feb 02 2006 |
| Draft BIRD100.2 | .txt | Arpad Muranyi | Intel Corporation | Jan 10 2006 |
| IBIS Roadmap for Versions 4.2 and 5.0 | .ppt | Michael Mirmak | Intel Corporation | Jan 10 2006 |
| IBIS Specification Direction | .pdf | .ppt | Michael Mirmak | Intel Corporation | Nov 17 2005 |
| IBIS Specification Proposal Summary | .ppt | Michael Mirmak | Intel Corporation | Oct 26 2005 |
| Return Paths Compared | Michael Mirmak | Intel Corporation | Oct 20 2005 | |
| Quiet Line Experiment | Arpad Muranyi | Intel Corporation | Oct 06 2005 | |
| Quiet Line Experiment (Updated) | Arpad Muranyi | Intel Corporation | Oct 06 2005 | |
| The Concerns about BIRD 95.6 from Cadence | Lance Wang | Cadence Design Systems | Oct 06 2005 | |
| Using IBIS in Non-ideal Power Supply Situations | Lance Wang | Cadence Design Systems | Oct 06 2005 | |
| General CMOS Small Signal Circuit | Lance Wang | Cadence Design Systems | Oct 05 2005 | |
| Quiet-Line Simulation Results with Power or Ground Changes Using IBIS and HSPICE Transistor-Level Models | Lance Wang | Cadence Design Systems | Oct 05 2005 | |
| Reply to Cadence Quiet-Line Simulation Results | .ppt | Zhiping Yang | Cisco Systems | Oct 05 2005 |
| Effect of Pin Parasitics on SSN | .ppt | Ambrish Varma | North Carolina State University | Sep 29 2005 |
| Power and Ground Changes Gives Different Quiet-line Simulation Results | Lance Wang | Cadence Design Systems | Sep 29 2005 | |
| Split C-comp for Quiet Line | Lance Wang and Shangli Wu | Cadence Design Systems | Sep 08 2005 | |
| BIRD95 Validation with Micron Output Buffer | Zhiping Yang | Cisco Systems | Aug 31 2005 | |
| Why The Ground Parasitic Should Be Removed for High-Speed Simulation Correlations Between HSPICE and IBIS | Zhiping Yang | Cisco Systems | Aug 31 2005 | |
| Power/Ground Pin Parasitics for SSN Simulations - A Literature Review | .ppt | Ambrish Varma | North Carolina State University | Aug 26 2005 |
| BIRD95 Impedance Experiments | .ppt | Michael Mirmak | Intel Corporation | Aug 11 2005 |
| Test Cases and Results using BIRD95 Composite Current Method | Lance Wang | Cadence Design Systems | Aug 04 2005 | |
| BIRD100 - A Series of Package Choices | .ppt | Michael Mirmak | Intel Corporation | Aug 03 2005 |
| Draft BIRD100, Rev. 1 | .txt | Michael Mirmak | Intel Corporation | Aug 03 2005 |
| IBIS Simultaneous Switching Output Simulations Criticality | Antonio Girardi | STMicroelectronics | Jul 19 2005 | |
| ICM Interfacing Options, Ver. 4 | .pdf | .ppt | Michael Mirmak | Intel Corporation | Jun 12 2005 |
| IBIS Gate Modulation Effect Proposal | Antonio Girardi | STMicroelectronics | May 30 2005 | |
| ICM Interfacing Options, Ver. 3 | .pdf | .ppt | Michael Mirmak | Intel Corporation | Mar 10 2005 |
| Macromodeling, AMS and the Future of IBIS | Michael Mirmak | Intel Corporation | Feb 17 2005 | |
| ICM Interfacing Options | .ppt | Michael Mirmak | Intel Corporation | Oct 07 2004 |
| Draft IBIS 4.1 Specification Section 6b | .ibs | Lynne Green | Green Streak Programs | Jun 10 2004 |
| Format Proposal for User Defined Measurements | .ppt | Michael Mirmak | Intel Corporation | May 13 2004 |
| User Defined Measurements and Test Loads in IBIS | .ppt | Arpad Muranyi | Intel Corporation | May 06 2004 |
| Multilingual Model - [Circuit Call] References | .ppt | John Angulo | Mentor Graphics | Apr 08 2004 |
| Multilingual Model - Clarification of Uniqueness for External Model Port Names | .zip (ppt) | Ian Dodd | Mentor Graphics | Mar 25 2004 |
| Multilingual Model - Digital Port Issues | .ppt | Ian Dodd | Mentor Graphics | Mar 25 2004 |
| Proposal for New Futures Task Group | .ppt | Michael Mirmak | Intel Corporation | Jan 30 2004 |