============================================================================== IBIS INTERCONNECT TASK GROUP Mailing list: ibis-interconnect@freelists.org ============================================================================== Attendees from July 9, 2025 Meeting (* means attended at least using audio) ANSYS Curtis Clark, Wei-hsing Huang, Juliano Mologni Arista Networks Jim Antonellis Broadcom James Church Chipletz Stephen Newberry Intel Corp. Michael Mirmak*, Xiaoning Ye Keysight Technologies Ming Yan Marvell Steve Parker MathWorks Walter Katz* Micron Technology Justin Butterfield Siemens EDA Weston Beal, Arpad Muranyi*, Randy Wolff* Simberian Yuriy Shlepnev ST Microelectronics Aurora Sanna Synopsys Ted Mido, Edna Moreno University of Illinois Jose Schutt-Aine Michael Mirmak convened the meeting. No patents were declared. The minutes from the previous meeting were not yet available for review. Michael showed a simple slide summarizing how connectivity is established relative to Physical and Logical declarations. Several fundamental cases make the distinctions very clear: devices (like BJTs) don't separate Physical and Logical definitions, but connectors tend to separate these completely. Packages may or may not distinguish between Physical and Logical connectivity depending on whether the package information is provided separately from the whole component (or the die). Arpad Muranyi suggested that the fourth case is a package combined with silicon - die side vs. ball side, where the ball side could be put on any board. One side has fixed connectivity (the die side), the other may be connected flexibly. Walter Katz stated that Physical definitions take precedence (we're overthinking this problem); pin number is the ultimate determinant of connectivity. Logical identifiers are for when the Physical ones are not provided. He suggested that text similar to the following be added to the proposal: "The model maker shall assume that the tool will use the Physical as higher precedence than Logical." Walter added that the assumption is that all the pin numbers match between components when establishing connectivity. For instance, the nets for a socket connecting to a PCIe card are where pin numbers will match (an exception is where smaller connectors are used within a larger system, and so the system may have mismatched numbers). The connector on the board and the DIMM mate exactly for memory connections. Michael replied that both sides assume a memory context. But one can use, say, Ethernet jacks and plugs for non-Ethernet applications; the connectivity cannot be assumed from Logical associations. Walter mentioned the common error of using names formatted as A1, A2, A3 on one side vs. 1A, 2A, 3A on the other. Michael cited the concept of a "bag of parts", where individual connectors, cables and other component models may be provided as part of a system design, but without a system connectivity "map" (a netlist or schematic), connectivity cannot be unambiguously established. This comes from outside the models. Walter replied that, for PCB design, pre-layout stages use Logical names, but for post-layout everything keys off of pin numbers. Arpad noted that his original question was about what "Physical" even means. For example, for a 4-wire ribbon cable, on the end one of a physical cable, the first wire (pin 1) of the four at one side should be connected to pad 1 of an integrated circuit. How do you know this? Walter stated that "first" is not a physical identification - Physical is either an X, Y coordinate or a pin number. Arpad asked whether Physical describes itself or describes to what it should be connected to? Walter replied that Physical describes itself. Arpad replied that this is the problem: an EMD file cannot be created from the header of the component alone. Randy Wolff suggested that one always does both or one/the other, depending on the information available. Arpad asked whether both of those are called Physical connections. Walter answered that, with EMD, one port of the EMD model is an EMD pin number (pin name). In ODB++, the pin number is A1, while the net name may be DQ_P0,etc.. The location of the probes is at the pins. You measure based on physical layout. Michael answered that this assumes the schematic is being created and read by humans; subsets may be connected, but not whole systems, through automation. Yet this seems to be the goal. Walter replied that some carbon-based involvement is assumed at some level, yes. Arpad added that interconnects end at some level end (pin 1 always connects to pin 1 and not pin 100, for example); the footprint of a chip, etc. always uses the same pin on both sides. The exception is end of a board trace, and you want to connect a BNC connector, then you have to know that the x,y,z point of the trace end belongs to the connector. Bare ribbon connector wire does not have this information. Are both of these types of descriptions called Physical? Walter replied that each side only specifies what's on its own side. For Example 1, Arpad asked what is the meaning of A.1? Walter replied that the A side is side CPU, B side is the sensor side; JEDEC standard shows this. Michael asked whether the side definition would come from JEDEC. Walter answered that Physical does come from JEDEC in this example. You can say this particular cable always comes this way, unlike Ethernet. Michael noted that, in this example, Net and Side seem to be referring to the full system. Walter noted that he was thinking of a mezzanine connector with an understood orientation. Arpad asked which pin or ball of the CPU this was connecting to. Randy noted that the model maker only has the cable, not the system. Arpad suggested that you can have a variant of this where you know all of this information; how can we associate a specific CPU pin with this particular connector pin? Walter replied that the CPU is on a board with pins A1, etc.; pins are on the connector, not the board the connector is on. Arpad sked whether we can distinguish (indicate) in this syntax that pin A1 is the end of a wire, but also connecting to a CPU pin. In EMD, we want to say that this component will be connected to something else; which port goes to which pad or pin? We are looking for a way to explain the meaning of A.1. What's the context? Walter replied that, as a component, one is talking about one's own context. Michael noted hat some of the examples are not EMD-compatible. Arpad re-stated that the original issue was Physical vs. Logical definitions. Should we use Physical for both cases? If we use the refdes syntax, we know one thing, but if we use pin numbers we have something else. Does Physical have multiple meanings? Walter replied that, for Physical, you (as a component) are always describing yourself. Arpad asked in response whether we are sure about this. The team discussed the formatting for specific device references, including the "refdes.pinnumber" syntax. Next time the team will focus on the meaning of and support for dot notation. Arpad moved to adjourn; Randy and Walter simultaneously seconded. The meeting adjourned without objection.