DATE: 1/18/00 SUBJECT: 1/14/00 EIA IBIS Open Forum Meeting Minutes VOTING MEMBERS AND 2000 PARTICIPANTS LIST: 3Com (Roy Leventhal) Applied Simulation Technology Raj Raghuram* Avanti (Nikolai Bannov) Cadence Design Mike LaBonte* Cisco Systems (Syed Huq) Compaq Bob Haller* Cypress (Rajesh Manapat) EMC Corporation (Fabrizio Zanella), Fairchild Semiconductor (Craig Klein) H.A.S. Electronics (Haruny Said) Hewlett Packard (EEsof, etc.) (Karl Kachigan) HyperLynx (& Pads Software) Matthew Flora*, Kellee Crisafulli*, John Angulo* IBM Michael Cohen* Incases (Werner Rissiek) Intel Corporation Stephen Peters*, Arpad Muranyi* LSI Logic (Larry Barnes) Mentor Graphics (& Veribest) Bob Ross* Mitsubishi (Tam Cao) Motorola Ron Werner* National Semiconductor Milt Schwartz* North East Systems Associates (Edward Sayre) NEC (Hiroshi Matsumoto) Nortel Networks (Calvin Trowell) Philips Semiconductor D.C. Sessions* (& VLSI Technology) Quantic EMC (Mike Ventham) Siemens (Gerald Bannert) SiQual (Scott McMorrow) Texas Instruments Stephen Nolan*, Time Domain Analysis Systems (Dima Smolyansky) Viewlogic Systems Chris Rokusek*, Guy de Burgh*, (Jon Powell) Via Technologies (Weber Chuang) OTHER PARTICIPANTS IN 2000: EIA (Cecilia Fleming) Molex Incorporated Gus Panella* In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode January 31, 2000 - DesignCon 2000 IBIS Summit Meeting (No Bridge) All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS AND MEETING QUORUM Bob Ross started the meeting and stated that there were the required number of companies present to establish a quorum. Stephen Nolan of Texas Instruments introduced himself. He is an application engineer in the logic products group and is involved with IBIS model development. Another engineer in the group is also expected to become active. Stephen is also leader of a JEDEC JC-40.4 group and is active in other groups as well. One of Stephen's interests is to learn more about IBIS and propose a BIRD enhancement to deal with the AVC dynamic output control circuitry which uses voltage feedback to control driver output impedance. This technology is being implemented by several companies. Stephen plans to send out to the IBIS reflector a web address describing the technology. MEMBERSHIP UPDATE AND TREASURER'S REPORT Bob Ross does not have any recent updates. He announced that Cecilia Fleming has sent out the year 2000 membership invoices. REVIEW OF MINUTES AND AR'S Bob Ross reported that Michael Cohen had submitted a request that the December 17, 1999 Minutes be amended to include the actual s2ibis3 funding vote. Bob noted that the recorded vote was as follows and will add this to the minutes: YES - Cisco Systems, HyperLynx, IBM, National Semiconductor, NO - 3Com, Applied Simulation Technology, Cadence Systems, Intel, Motorola, Time Domain Analysis Systems, VLSI Technology (Philips Semiconductor) ABSTAIN - Compaq, Fairchild Semiconductor, Mentor Graphics, Viewlogic Systems NOT PRESENT - Texas Instruments Bob also will make a minor editorial correction in the list of participants. The December 17, 1999 IBIS Open Forum Meeting Minutes were approved with the above changes and the amended minutes will be uploaded [Done]. The AR's will be discussed during the meeting. MISCELLANY/ANNOUNCEMENTS Bob Ross noted that the year 2000 participation list starts again this year. Bob keeps this information to document industry-wide support and interest. Last year we had 33 official member companies. We also had about 88 people from member companies and about 140 people total who participated in at least one meeting. This represents a modest growth from previous years. Currently we have 31 members since Mentor Graphics now includes VeriBest, and Philips Semiconductor now includes VLSI Technology. PRESS AND WEB PAGE UPDATES Bob Ross reported that Syed Huq made a lot roster changes and upgrades to the membership list starting at year 2000. Some of these include an address change for TDA Systems, and the combining of company information for Philips Semiconductor and Mentor Graphics as noted above. Also Syed added that web links to the home page were added to all companies which did not supply links. Members who want the links directed elsewhere can contact Syed. Bob reported that a reference to IBIS exists in "Implementing an Internal Signal Integrity Department" by Lynne Green and Lee Richey in the January 2000 issue of Printed Circuit Design, pp. 24-28. Also, Bob reported that Jon Powell will be giving two presentations at the PCB Design Conference West, March 20-24, 2000 titled: "Introduction to the Use and Effectiveness of IBIS Models for SI Simulation", and "Writing and Qualifying IBIS Models". NEW MODELS AVAILABLE, LIBRARY UPDATE Bob Ross had no report. OPENS FOR NEW ISSUES None INTERNATIONAL/EXTERNAL PROGRESS - IEC 62014-1 (IBIS Version 3.2) - Bob Ross noted that the international representative has been out, and we have not yet been able to find out the status on the formal ratification of IBIS Version 3.2 as IEC 62104-1. - pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuits (IMIC) - Bob Ross reported that the December 21, 1999 deadline for comments had passed for Version 1.2. Mike LaBonte stated that the group is meeting in January and will probably accept late comments. - IEC PWI 93-1 Models of Integrated Circuits for EMI Behavioral Simulation (formerly designated as IEC 93/67/NP IBIS and EMC Simulation) - Bob Ross had no further report. - JC-16.2 Subcommittee: Modeling and Test - D.C. Sessions reported that committee plans to issue a set of reference simulations for DDR. He also has some meetings regarding using IBIS in a standards context for JEDEC specification issues. D.C. stated that there are some technologies such as AGP4X which have features not covered by IBIS. Bob Ross noted that IBIS emerged primarily to capture information for simulation, but has always included some specification information. There has always been pressure to add more specification limit information. Later, D.C. stated that he and Bob have been working on a joint JEDEC/IBIS meeting to be held on Thursday afternoon, February 3, 2000. A formal JEDEC JC-42.3 Working Group meeting is held on Friday, February 4, 2000. The smaller meeting is intended to be a less formal working group session to discuss and coordinate some newer technology issues common to both organizations. D.C. plans for about 10 to 12 people total to be held in a (small) room at Philips in San Jose, California. The planning has just been occurring recently, so meeting details and participation is still not finalized. From the IBIS side, Bob has already invited several people involved with input modeling proposals (an issue of common interest) and wants to expand the participation to include an EDA representative from the IBIS member companies. D.C. is inviting JEDEC participants from semiconductor vendors. While more details will emerge in the following weeks as the participation list is confirmed, D.C. stated that some final planning may occur after the IBIS Summit Meeting on Monday, January 31, 2000. (Bob is following through on inviting EDA vendor participants.) DESIGNCON 2000 IBIS SUMMIT PLANNING Bob Ross restated that the IBIS Summit meeting is being held on Monday, January 31, 2000 in Santa Clara, California. The IBIS Open Forum is listed again as an Associate Sponsor of DesignCon 2000 which means that DesignCon is providing the meeting room and refreshments and also booth space. National Semiconductor is sponsoring the luncheon. Milt Schwartz commented that he sent out the second announcement and also estimates about 27 signups so far. He is planning for 50. Several people stated that they did not realize that the announcements also requested signing up for the meeting. After some discussion, Bob stated that we plan to send another announcement shortly for signup. We will finalize the agenda and send it out later, one week before the meeting. Bob noted updates in the program. We dropped the Accuracy discussion since the most recent work is an upgrade to the test board which may or may not be available at the IBIS Booth. A presentations by Richard Mellitz has been added. Updated Program: "Model Design: Tables and Equations" - Lynne Green, Hyperlynx "Connector Model Specification" - Gus Panella, Molex "Input Receiver Modeling" - Donald Telian, Cadence "Using Statistical Methods to Characterize Receivers to Determine the Applicability of Receiver Modeling Standardization" - Richard Mellitz, Intel "Discussion on the Future of IBIS" - Stephen Peters, Intel Bob stated that he will plan the Model Design presentation and Connector discussion in the morning and the input modeling and IBIS Futures discussion in the afternoon. Ad Hoc presentations will be welcome. The recent trend of having fewer presentations to allow more time for interactive discussions has worked well in recent IBIS Summit meetings. The EIA IBIS Open Forum will have a booth at DesignCon. Bob Haller stated that he is arranging a demonstration and test board to demonstrate some techniques to measure critical parameters on a high speed connector. He may also have an accuracy test board, if it is ready, for discussion and illustration purposes. He mentioned several people who are working on it. Equipment will be supplied by Agilent. Bob H. wanted to pass out the latest copy of the pending IBIS Connector Specification document. Ron Werner pointed out that we should not pass out preliminary work. However, we can have some copies available for review at the booth. Also, the document is large, and we can provide the links to download the document. Bob R. note that Jon Powell is collecting IBIS logo signs to be used as a backdrop for the booth (being donated by Viewlogic). Jon will use the member company signs from last year if updated ones are not received. New member companies are welcome to send Jon their signs. DATE2000 IBIS SUMMIT PLANNING Bob Ross reviewed that the DATE2000 IBIS Summit meeting associated with the Design Automation and Testing in Europe conference is planned to be held in Paris, France on Friday, March 31, 2000. The meeting is planned to run from morning to early afternoon. Incases, Viewlogic and Mentor Graphics are co-sponsors. Bob plans to have a notice sent out in the next several weeks for early planning and travel arrangement approval. COOKBOOK STATUS Stephen Peters had no report. Ron Werner asked what the future plans are, and Stephen responded that on a low priority basis, some Version 3.2 features will be added. Stephen Nolan commented that he is closely reviewing the Cookbook and may be able to help in an updating the document. IBIS MODEL REVIEW COMMITTEE DISCUSSION Matthew Flora reported that he has received a model from Honeywell for review. Matthew needs to update the distribution list before sending out this model. Matthew Flora had previously sent out a model from Galileo Technology at end of last year for review. IBIS FUTURES (IBIS-X, API, BIRDxx) Stephen Peters introduced the IBIS-X proposal to deal with some current issues. IBIS lacks some critical analysis factors and does not handle well the power and ground distribution and return path. One unattractive option is to issue encrypted Spice models. The IBIS-X proposal uses some major concepts of IBIS such as the I-V and V-T table description for buffers. It also uses submodels. It adds a nodal descriptions and will be able to deal with pin to pin coupling. D.C. Sessions stated that package parasitics are becoming the dominant factor in high speed design. He emphasized that board level EDA tools needs to handle this better. Stephen added that an exchange format may be developed to support newer constructs that have not been standardized. The overall IBIS-X proposal is not intended to be backwards compatible with IBIS Verison 3.2. Gus Panella asked, and Stephen responded that this proposal is planned to be in a separate document. Bob Ross noted that some good structural comments were provided by Al Davis. Matthew Flora indicated that Al has examples of the methodology and some macro extensions to support existing IBIS keywords for backwards compatibility. Bob welcomed a suggestion of having Al do a presentation at the IBIS Summit Meeting on January 31, 2000. Stephen also invited putting this information on the IBIS reflector. IBISCHK BUGS Bob Ross noted that we are still deferring discussion on BUG34. We also have several other reported bugs and enhancements. One old report is that repeated voltage values in I-V tables are not reported. Stephen Nolan recently reported that the 8.3 file size rule is not checked anymore using ibischk3 when the file is designated by Version 2.1. We need to issue BUG reports for tracking, but these fixes have not been a high priority item in recent months. Matthew Flora asked who has the source code. Bob responsed that Atul Agarwal still controls the master copy and also has unreleased fixes for BUG36 and BUG37. Matthew and Chris Rokusek have also made significant technical enhancements to the source code in the past. CONNECTOR PROPOSAL REVIEW During the discussion, Kellee Crisafulli stated that Version 0.93 of the Connector Specification had just been uploaded. A number of editorial suggestions have been incorporated. However, no major technical based on recent suggestions have been incorporated. The new document divides the information into sections similar to IBIS Verison 3.2. Kellee has added an Introduction, Statement of Intent, Change Section, and Tree diagram. He did re-position the keywords for [Manufacturer], [Web], [Email], and [Redistribution] to be under the [Define_Cn_Model_Family]. Kellee also changed the order of keywords for clarity. To avoid confusing the discussion at this meeting, he did not pre-announce the new document. D.C. Sessions questioned whether the Connector Specification was outside the charter of the IBIS Open Forum, which has been concerned about a single IBIS document. Bob Ross thought that EIA and ANSI would not have a problem with the work we are doing with Connectors. Bob Ross opened the Connector Specification by stating that there has been much progress in recent months. The enhanced matrix discussion had been added. There appears to be general consensus on the current scope of the Connector Specification (deferring frequency dependent losses until later) and using the coupled matrix structures similar to those in IBIS Version 2.1. Bob reviewed some of his technical comments and responses issued on the IBIS reflector. Many, but not all of the comments are captured below. We attempted to provide better understanding, but not necessarily any final resolution on the point that were raised. Bob questioned why we needed to limit the [Begin_Cn_Model_Family] to one per file. This is inconsistent with other top-level IBIS keywords. While manufacturers might in practice limit one per file for distribution, a design file might include many connectors for file efficiency. Also, the connectors of a design might be exported in one file. Kellee pointed out that this would not be a limitation. The new [Begin_Cn_Model_Family] could be used to bracket the body from the header information. Bob thought this might be a good interpretation. Bob questioned the [Begin_Cn_Model_List] Max_Slew_Time term. Bob thought that what was intended was to document the maximum slew rate which would then correspond to the minimum slew time (or transition time) for which the model is considered valid. Kellee and Gus Panella commented that the connector committee had spent time discussing the terminology and thought that they had come to a resolution. Others had suggestions. Kellee and Gus agreed to take the suggestions and provide an alternative proposal. The [Begin_Cn_Model] syntax was discussed. Gus Panella confirmed that there were situations where only the internal [Begin_Cn_Auto_Map] is used and there is no need for the required ModelPinMap and ModelPhyMap parameters on the command line. Bob noted that other similar commands only have the model_name entry on the command line. Gus had suggested on the IBIS reflector that we might consider requiring a default pin map and physical pin map for simulators not supporting the [Begin_Cn_Auto_Map] keyword. Bob noted that other similar commands only have the model_name entry. Subparameters could also be considered. Kellee commented that subparameters mixed with the topology lines (Cn_Section, Cn_Stub) might be confusing. Bob noted that no keywords in this document have subparameters. Bob stressed that this type of issue needs to be resolved because it would arise again as a parser development question regarding missing references and what errors to issue. Bob also commented that the Cn_Series should support cascading sections in series on the same line. This would be consistent with Cn_Stub which supports cascaded section. This would also simplify the syntax rules and implementation. Putting Cn_Series sections on separate lines would still be permitted. We debated the need for providing a 100,000 point conductor size limit. Bob felt that actual conductor topologies should determine the limit. Kellee and others noted that a limit was needed so that EDA vendors have an upper bound on memory allocation. Plus it could be used by the parser to check against mistaken entries. We talked about other maximums. Bob would be comfortable with just a recommendation statement or dealing with this as a parser test warning message. Bob just noted that the [Begin_Cn_Auto_Map] might allow some syntax violations - such as indices of the same value. Also, the parameter method needs to be reviewed. Kellee indicated that VARIABLE was an appropriate place holder for a variable. Bob questioned why only .jpg and .txt images were permitted under [Begin_ Cn_Model_List]. Gus argued that limiting the formats was intended to be helpful to EDA tool vendors by limiting the choices to be supported. Other formats were suggested. When Bob questioned the EDA Vendors, he got several answers. Kellee indicated that the .gif format was rejected because of reader licensing issues. Bob's main point is that he would prefer recommended, but not required formats. Otherwise, the parser would have to provide an extension test and reject models with unapproved extensions. Bob closed the discussion by noting that we plan more discussion at the IBIS Summit Meeting. Bob also welcomes continued reflector discussion. Kellee will continue to be the editor of the Connector Specification and may incorporated changes based on this and other discussions. BIRD62.2 ENHANCED CHARACTERIZATION OF RECEIVER THRESHOLDS BIRD63.2 DOCUMENTATION OF RECEIVER SETUP AND HOLD TIMING CONDITIONS Bob Ross mentioned that we need to review these BIRDs since they will be coming up for a vote after the DesignCon IBIS Summit Meeting. NEXT MEETING: The next Meeting is the IBIS Summit Meeting from 8:30 AM to 5:00 PM on Monday, January 31, 2000 associated with DesignCon 2000 in the Westin Hotel in Ballroom C. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentor.com Modeling Engineer, Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515 sjpeters@ichips.intel.com Senior Hardware Engineer, Intel Corporation M/S JF1-209 2111 NE 25th Ave. Hillsboro, OR 97124-5961 SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259 gdeburgh@viewlogic.com Senior Manager, Viewlogic Systems 1369 Del Norte Rd. Camarillo, CA 93010-8437 LIBRARIAN: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jpowell@viewlogic.com Senior Scientist, Viewlogic Systems 1369 Del Norte Rd. Camarillo, CA 93010-8437 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Signal Integrity Engineer, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: Matthew Flora (425) 869-2320, Fax: (425) 881-1008 mbflora@hyperlynx.com Senior Engineer, HyperLynx, Inc. 114715 N.E. 95th Street Redmond, WA 98052 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2/3 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eia.org/eig/ibis/ibis.htm Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. ==============================================================================