AGENDA –EUROPEAN IBIS SUMMIT MEETING

Wednesday, May 10, 2017

IEEE SPI 2017

GRAND HOTEL DINO

C.so Garibaldi, 20 28831

Baveno (VB), Italy

Room: Sala Marte (main conference room)

Sponsors: ANSYS

CST Computer Simulation Technology AG.

Mentor, A Siemens Business

Zuken

(Minutes) | (Zip download of all files)

13:30 REFRESHMENTS AND SIGN IN

13:45 WELCOME AND INTRODUCTIONS
Michael SCHAEDER, Zuken, Germany

14:00 Accurate Macromodels of Output Buffers with Pre-/De-emphasis

Gianni SIGNORINI*, Claudio SIVIERO**,

Igor Simone STIEVANO**, Stefano GRIVET-TALOCIA**,

*Intel Corporation, Germany; **Politecnico di Torino, Italy

[Presented by Gianni SIGNORINI, Intel Corporation; Germany]

14:30 Compact Multivariate Surface Approximations for Power-aware I/O models

Claudio SIVIERO*, Stefano GRIVET-TALOCIA*,

Gianni SIGNORINI**, Igor Simone STIEVANO*

*Politecnico di Torino, Italy; **Intel Corporation, Germany

[Presented by Claudio SIVIERO, Politecnico di Torino, Italy]

15:00 IBIS Update

Mike LABONTE, Signal Integrity Software (SiSoft),

[Presented by Michael Schaeder, Zuken, Germany]

15:30 COFFEE AND REFRESHMENTS

15:45 Interconnect Modeling Using IBIS-ISS and Touchstone

Michael MIRMAK, Intel Corporation, USA

         [Presented by Stefan PARET, CST AG, Germany]

16:15 IBIS Extensions for Turn-around Cycle Simulations

         Nitin BHAGWATH*, Arpad MURANYI*, Randy WOLFF**

         *Mentor, A Siemens Business, USA

         **Micron Technology, USA

         [Presented by Nitin BHAGWATH, Mentor, A Siemens Business; USA]

16:45 OPEN DISCUSSION

17:15 CLOSING REMARKS
Michael SCHAEDER, Zuken, Germany

17:20 END OF MEETING

- Thank you for your participation