FILE: a111312.txt
TITLE: Agenda
TYPE: .txt
AUTHORLAST: 
AUTHORFIRST: 
COMPANY: IBIS Open Forum
DATE: Nov 13 2012
LOCATION: Hsinchu, Taiwan

FILE: m111312.pdf
TITLE: Minutes
TYPE: .pdf
AUTHORLAST: 
AUTHORFIRST: 
COMPANY: IBIS Open Forum
DATE: Nov 13 2012
LOCATION: Hsinchu, Taiwan

FILE: mirmak.pdf
TITLE: IBIS 5.1 - An Overview
TYPE: .pdf
AUTHORFIRST: Michael
AUTHORLAST: Mirmak
COMPANY: Intel Corporation
DATE: Nov 13 2012
LOCATION: Hsinchu, Taiwan

FILE: ross.pdf
TITLE: IBIS Parser Update
TYPE: .pdf
AUTHORFIRST: Bob
AUTHORLAST: Ross
COMPANY: Teraspeed Consulting Group
DATE: Nov 13 2012
LOCATION: Hsinchu, Taiwan

FILE: wang.pdf 
TITLE: IBIS Model Validation Review
TYPE: .pdf 
AUTHORFIRST: Lance
AUTHORLAST: Wang
COMPANY: IO Methodology
DATE: Nov 13 2012 
LOCATION: Hsinchu, Taiwan 

FILE: lin.pdf
TITLE: Chip PDN Model for Power Aware Signal Integrity Analysis
TYPE: .pdf
AUTHORLAST: W.C. Lin, Raymond Y. Chen and Haisan Wang
AUTHORFIRST: Jack  
COMPANY: Cadence Design Systems
DATE: Nov 13 2012
LOCATION: Hsinchu, Taiwan

FILE: hsuan.pdf
TITLE: IBIS-AMI, industry adoption, and current challenges
TYPE: .pdf
AUTHORLAST: Hsuan and TingHao Yeh
AUTHORFIRST: Naijen
COMPANY: ANSYS
DATE: Nov 13 2012
LOCATION: Hsinchu, Taiwan

FILE: kukal.pdf
TITLE: Designing DDR3 system using Static Timing Analysis in Conjunction with IBIS simulations
TYPE: .pdf
AUTHORLAST: Kukal, Zhangmin Zhong, Heiko Dudek
AUTHORFIRST: Taranjit  
COMPANY: Cadence Design Systems
DATE: Nov 13 2012
LOCATION: Hsinchu, Taiwan

FILE: pytel1.pdf
TITLE: Electronic Interconnect Challenges
TYPE: .pdf
AUTHORLAST: Pytel
AUTHORFIRST: Steve
COMPANY: ANSYS
DATE: Nov 13 2012
LOCATION: Hsinchu, Taiwan

FILE: pytel2.pdf
TITLE: The Evolution of DDR Memory and Overcoming Challenges of DDR3/4 Design
TYPE: .pdf
AUTHORLAST: Pytel
AUTHORFIRST: Steve
COMPANY: ANSYS
DATE: Nov 13 2012
LOCATION: Hsinchu, Taiwan

FILE: liu_jt.pdf
TITLE: Efficient End-to-end Simulations of 25G Optical Links
TYPE: .pdf
AUTHORLAST: Liu*, Fangyi Rao*, Sanjeev Gupta** and Amolak Badesha**
AUTHORFIRST: Jing-Tao
COMPANY: Agilent Technologies* and Avago Technologies**
DATE: Nov 13 2012
LOCATION: Hsinchu, Taiwan

FILE: liu_p.pdf
TITLE: Using Latency Insertion Method to Handle IBIS models
TYPE: .pdf
AUTHORLAST: Liu*, Jilin Tan* and Jose E. Schutt-Aine**
AUTHORFIRST: Ping 
COMPANY: Cadence Design Systems* and University of Illinois at Urbana-Champaign**
DATE: Nov 13 2012
LOCATION: Hsinchu, Taiwan