Subject: RE: Duty Cycle
From: Lorang, David D (david.d.lorang@intel.com)
Date: Thu Sep 20 2001 - 16:34:26 PDT
Tim,
I think you have it right.
Let's take the example of a clocked synchronous design where a chip has a
some clock input and a data output. Suppose output data changes on every
rising clock edge. You might have a specification for Tco delay of maybe
2ns, or whatever, for both rising edge and falling edge data.
Then suppose you are using a SPICE simulation of some buffer to generate
your voltage vs. time data to create an IBIS file. You would might run two
simulations each where the rising edge of the input clock starts at time
0ns: one for rising data, one for falling data. The two simulations would
generate two output V-T tables that would have their rising and falling
edges correlated, because they both were timed from a clock starting at the
same time (0 ns). From the tabular output files, for those two sims you
could create two IBIS V-T tables.
Where exactly the output edges occur is dependent on internal buffer delays,
and that is not important, but where the two edges occur relative to each
other is important. So you make sure you handle both tables in the same way
when you import them into the IBIS file. You may decide to eliminate the
internal buffer delay--commonly done to make sure that the tables contain
mostly edge data--and if you took 1.5ns out of the front of one VT table,
you would want to take the same amount out of the other. All of this is
just to make sure that the IBIS file retains information concerning the
timing relationship between the two edges. For this example so far I am
assuming only one load configuration, perhaps, a 50 Ohm resistor to ground.
For the other load configuration (resistor to supply), you would go through
the same steps again and observe the same precautions. In the end you would
have four V-T tables, with their waveforms all correlated. So, in summary,
you need to correlate rising and falling edges in the same way you correlate
the two load configurations.
Have I answered your question?
Dave Lorang
-----Original Message-----
From: tcoyle [mailto:TCoyle@pdcme.fairchildsemi.com]
Sent: Thursday, September 20, 2001 12:34 PM
To: ibis-users@eda.org
Subject: Duty Cycle
Dear List,
I have some questions regarding Bird 68.1 and duty cycle. I understand
that IBIS does not guarantee propogation delays,
but if the rising and falling waveform data is correlated then duty
cycle can be maintained. I'm not sure I understand how you
taking rising /falling data to ensure duty cycle? Is it a matter of
doing the same transient analysis for rising/falling edges?
Thank you for any information provided
Tim
This archive was generated by hypermail 2b28 : Thu Sep 20 2001 - 16:52:42 PDT