Subject: RE: Duty Cycle
From: Todd Westerhoff (twester@hhnetwk.com)
Date: Tue Sep 25 2001 - 15:15:30 PDT
Dave, et al.,
Well, now I realize my comment was out of context, as I was referring to
IBIS as-is-in-current-practice, instead of IBIS as-it-would-be with BIRD
68.1. I can see that BIRD 68.1 would allow IBIS models to do a better job
of predicting ISI caused by duty cycle assymetry in the driver.
If I'm reading the BIRD correctly, this is a modeling issue, and not a tool
issue, correct? It seems to me there are no tool changes required,
providing the SI tools do not "alter" the V/T data in the IBIS waveforms
prior to their use.
If that were the case, it would seem to me that we could start producing
models to the updated spec immediately.
Todd.
Todd Westerhoff
SI Engineer - Hammerhead Networks
5 Federal Street - Billerica, MA - 01821
email:twester@hhnetwk.com - ph: 978-671-5084
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-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On
Behalf Of Lorang, David D
Sent: Monday, September 24, 2001 12:14 PM
To: 'Jon Powell'; Lorang, David D
Cc: ibis-users@eda.org
Subject: RE: Duty Cycle
Jon,
I'm not sure I understand what you are disagreeing with, but let me take
another shot an see if I can clear things up a little more. Please
understand that although originally it wasn't clear in IBIS how the timing
between rising and falling edges were related, BIRD 68.1 was written to
clarify that some information could be conveyed in the IBIS file regarding
the relationship between rising and falling edges (Rising vs. falling edge
timing will affect the duty cycle of a periodic waveform.) So before BIRD
68.1, it was no surprise that simulation engines interpreted the waveform
data in a variety of ways. Even now that BIRD 68.1 is approved, it is
probably safe to say that simulation engines still interpret the waveform
data in a variety of ways. Any changes that do happen won't occur overnight.
Hence IBIS, even with BIRD 68.1 applied, cannot guarantee that, for example,
the duty cycle of a waveform will come out as expected, (i.e. matching what
is happening in the silicon.) It is likely that the waveform timings will
often still need to be "manually" adjusted, and there are tools in at least
some simulation engines to do that.
What BIRD 68.1 does do is to specify that the relative timing information
will be there in the IBIS file, so that simulation engine developers at
least have a chance (in a specified, and perhaps more automated manner) to
eventually maintain timing relationships between rising and falling edges.
So now, at least, the hooks are there.
Dave Lorang
-----Original Message-----
From: Jon Powell [mailto:jpowell@innoveda.com]
Sent: Saturday, September 22, 2001 9:01 AM
To: 'Lorang, David D'
Cc: ibis-users@eda.org
Subject: RE: Duty Cycle
I have to disagree.
This isn't how IBIS is defined and speifically isn't how most simulation
engines interpret the waveform data.
The Waveform data cannot be used to specify duty cycle, however, this is
an option in most native IBIS simulators and you should contact your
simulator vendor for specifics on implementing different duty cycles
for different clocks etc.
regards,
Jon Powell
Innoveda Consulting Services
-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On
Behalf Of Lorang, David D
Sent: Thursday, September 20, 2001 4:34 PM
To: 'tcoyle'
Cc: ibis-users@eda.org
Subject: RE: Duty Cycle
Tim,
I think you have it right.
Let's take the example of a clocked synchronous design where a chip has a
some clock input and a data output. Suppose output data changes on every
rising clock edge. You might have a specification for Tco delay of maybe
2ns, or whatever, for both rising edge and falling edge data.
Then suppose you are using a SPICE simulation of some buffer to generate
your voltage vs. time data to create an IBIS file. You would might run two
simulations each where the rising edge of the input clock starts at time
0ns: one for rising data, one for falling data. The two simulations would
generate two output V-T tables that would have their rising and falling
edges correlated, because they both were timed from a clock starting at the
same time (0 ns). From the tabular output files, for those two sims you
could create two IBIS V-T tables.
Where exactly the output edges occur is dependent on internal buffer delays,
and that is not important, but where the two edges occur relative to each
other is important. So you make sure you handle both tables in the same way
when you import them into the IBIS file. You may decide to eliminate the
internal buffer delay--commonly done to make sure that the tables contain
mostly edge data--and if you took 1.5ns out of the front of one VT table,
you would want to take the same amount out of the other. All of this is
just to make sure that the IBIS file retains information concerning the
timing relationship between the two edges. For this example so far I am
assuming only one load configuration, perhaps, a 50 Ohm resistor to ground.
For the other load configuration (resistor to supply), you would go through
the same steps again and observe the same precautions. In the end you would
have four V-T tables, with their waveforms all correlated. So, in summary,
you need to correlate rising and falling edges in the same way you correlate
the two load configurations.
Have I answered your question?
Dave Lorang
-----Original Message-----
From: tcoyle [mailto:TCoyle@pdcme.fairchildsemi.com]
Sent: Thursday, September 20, 2001 12:34 PM
To: ibis-users@eda.org
Subject: Duty Cycle
Dear List,
I have some questions regarding Bird 68.1 and duty cycle. I understand
that IBIS does not guarantee propogation delays,
but if the rising and falling waveform data is correlated then duty
cycle can be maintained. I'm not sure I understand how you
taking rising /falling data to ensure duty cycle? Is it a matter of
doing the same transient analysis for rising/falling edges?
Thank you for any information provided
Tim
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