Subject: [IBIS-Users] How Do We model the parasitics of board. ?
From: Anshuli Goel (anshuli@india.ti.com)
Date: Thu Aug 22 2002 - 02:55:08 PDT
Hi All,
I have one querry ? The bondwire and pin capacitance is captured in R,L
and C of package in IBIS models but how do we take care of the load that
this buffer is going to drive outside the package ?
Does it need to be modeled ? If not than how that load is taken care
off while doing the simulation using IBIS models , 'coz the behaviour of
the I/O will change with different loads. ?
Regards
Anshuli Goel
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