Subject: RE: [IBIS-Users] Question about warning message
From: Henrik G. Madsen (hgm@vitesse.com)
Date: Mon Nov 18 2002 - 06:26:45 PST
If you have access to the Spice models, the below will normally solve the issue.
The BSIM3V3.x transistor model includes two sidewall diodes, one at the source and one at the drain terminal.
The Spice model (at least HSPICE) do not include any loss for these parasitic diodes.
As a consequence, a lot of current will begin flowing through these parasitic diodes, when a signal outside the rail voltages is applied to the PAD of the IO cell.
It is possible to 'turn off' the parasitic diodes in the BSIM3V3 NMOS/PMOS models by setting the below parameters to zero. This should only be done for the transistors closest to PAD in the I/O cell.
> Set JSW=0, CJ=0, CJSW=0, JS=0
Afterwards two discrete diodes should be added with the same size as the
transistor's source and drain terminal to include equivalent models of lossy diodes as the ones removed.
See example below
MTEST Drain Gate Source Bulk NCH3 L=0.50 W=28.00 AD=AreaD
+ PD=PerD AS=AreaS PS=PerS NRS=0.004 NRD=0.008
Becomes
MTEST Drain Gate Source Bulk NCH3_esd L=0.50 W=28.00 AD=AreaD
+ PD=PerD AS=AreaS PS=PerS NRS=0.004 NRD=0.008
dMTESTd Bulk Drain Diode area=AreaD PJ=PerD
dMTESTs Bulk Source Diode area=AreaS PJ=PerS
Where NCH3_esd is the same transistor as NCH3 except for that JSW=0,
CJ=0, CJSW=0, JS=0
/Henrik
-----Original Message-----
From: Ingraham, Andrew [mailto:Andrew.Ingraham@hp.com]
Sent: 18. november 2002 13:57
To: ibis-users@eda.org
Subject: RE: [IBIS-Users] Question about warning message
The warning about "extreme currents" probably means that you started
with inaccurate SPICE models.
The clamp diodes might be modeled (in SPICE) with unrealistically small,
or zero, series resistances, causing huge simulated currents at large
voltages beyond the supply rails.
Is it a problem? Yes and no. Most simulations shouldn't stray far into
these regions, and if they do, the huge currents generally steer things
back away from them. But it might mean that the simulated results do
not correctly show what happens in response to normal overshoot
transients.
The best way to fix it, is to correct the SPICE model, and start over.
Or measure how the device actually behaves and modify one or both models
accordingly.
Regards,
Andy
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