Subject: RE: [IBIS-Users] [Fwd: Validation of IBIS model]
From: Hazem Hegazy (hazem@qualim.com)
Date: Fri Jan 03 2003 - 23:51:32 PST
Hi,
I'm not sure of the model quality because of the followings:
- The number of point in the rising and falling edges is quit a
few before it reach steady state.
- There are Rising to gnd and Falling to VDD only V-T data, I
strongly recommend to have the other two (Rising to VDD and Falling to
ground).
- There is C_Fixture = 30p in the V-T data!! This is not
recommended while you generate the IBIS model wave forms, Please
regenerate the V-T tables without these capacitance.
- The C_comp value must be calculated and optimized in order to
get complete overlay with SPICE.
I think that all of these might be the cause.
One more thing, I noticed also from the validation you sent in this mail
the SPICE simulation reaches 2.7 as a steady state, while the IBIS
simulation reached 2.4 !!
BR,
Hazem Hegazy, M.Sc.
IBIS Modeling Engineer
QualiM
http://www.qualim.com/
Phone: (+20) 106052154
E-mail: hazem@qualim.com
-----Original Message-----
From: owner-ibis-users@server.eda.org
[mailto:owner-ibis-users@server.eda.org] On Behalf Of Anshuli Goel
Sent: Friday, January 03, 2003 4:48 AM
To: Ingraham, Andrew; ibis-users@eda.org
Subject: RE: [IBIS-Users] [Fwd: Validation of IBIS model]
Hi Andy
Thanx for the reply. That problem was actually because of timestep used
in simulation. I used a finer
timestep and my problem vanished.
But I have other problem. I am using the following setup for validating
the IBIS model. I hook up buffer
subckt once and once i hookup IBIS model with the rest of the setup.
Hi Andy
Thanx for the reply. That problem was actually because of timestep used
in simulation. I used a finer
timestep and my problem vanished.
But I have other problem. I am using the following setup for validating
the IBIS model. I hook up buffer
subckt once and once i hookup IBIS model with the rest of the setup.
The load changes from open circuit to matched load to short circiuit.
I see some ringing in matched load case with IBIS model simulation which
is not captured in SPICE
simulation . (For open load and short circuit load my results are
matching)
Why the results at matched load are not matching ?
The parameters for Tx is Z0=50ohm and Td=0.4ns
Input has 1ns risetime.
I am attaching the IBIS model and s2ibis2 script also.
Waveform with ringing (IBIS simulation)
Waveform without ringing(SPICE simulation using the subckt)
Regards
Anshuli
Ingraham, Andrew" wrote:
The "ringing" that I see with the SPICE model, looks more like some
sort of numerical oscillation that you
sometimes get in SPICE, and not real ringing. This numerical
oscillation is an uncommon but occasional
artifact of SPICE. If present, it can usually be eliminated by using
.OPTION METHOD=GEAR rather
than the default TRAPezoidal method.
You don't say how long the transmission line is, but it is probably
not causing the sub-nanosecond wiggles
that you are seeing on the SPICE model waveform.
If it isn't numerical oscillation, another place to look would be the
package parasitic modeling. Either the
IBIS model, or the simulator's use of it, might have simplified the
circuit representation of the package,
compared to the SPICE model.
Regards,
Andy
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