Subject: [IBIS-Users] differential output modeling
From: erik.van.der.ven@philips.com
Date: Tue May 13 2003 - 02:20:34 PDT
I have some problems on how to model a differential output.
In my case it is a lvpecl output.
The output swing is controlled by an internal feedback loop.
I noticed that when I simulate the pull-up/pull-down curves of the
non-inverting outputs the results are dependent on the termination of the
inverting output (resistor, voltage).
So these outputs obviously influence each other.
So question is what to do with the output that is not being modeled?
It seems that this situation is simular to LVDS outputs.
A method that I have seen is to connect a voltage source to the inverting
output, such that the sum of both voltages divided by 2 equals the common
mode voltage during normal operation.
I observe that the currents in the inverting output become very large and
are therefore still likely to influence the result of the non-inverting
output.
The motivation for this method was to approach behaviour during normal
operation. But I think this is not the case, since the outputs are forced
in a state that does not comply to the logic state as forced by the input
signal.
Has anyone experience with this?
With kind regards,
Ir. Erik van der Ven
Room DB1032
Business Line Networking Infrastructure
Philips Semiconductors BV
Gerstweg 2
6534 AE Nijmegen
The Netherlands
Phone: +31-24-3534334
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