Subject: RE: [IBIS-Users] On-die DIFFERENTIAL terminated buffer modeling
From: Henrik G. Madsen (hgm@vitesse.com)
Date: Thu May 22 2003 - 03:56:07 PDT
Hi
If you have the SPICE model for the LVDS cell, you can remove the build-in termination and model the LVDS input as normal.
Then afterwards, you can model the termination alone and add it to the IBIS file using the 'Series' model type.
Remember to add the termination pin info through the [Series Pin Mapping] keyword
I have tried to illustrate the final IBIS model below.
You have to be aware that certain IBIS tool still do not support the below approach fully.
Regards
/Henrik G Madsen
Example
.......
|
[Pin] signal_name model_name R_pin L_pin C_pin
|
pin1 LVDS_p LVDS_model
pin2 LVDS_n LVDS_model
|
[Diff pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max
|
pin1 pin2 NA NA NA NA
|
[Series Pin Mapping] pin_2 model_name function_table_group
|
pin1 pin2 term_model
|
|************************************************************************
[Model] term_model
Model_type Series
C_comp 0pF 0pF 0pF
|
[Temperature Range] 55.000 120.00 0.0000
[Voltage Range] 2.500V 2.300V 2.700V
|
|variable R(typ) R(min) R(max)
[R Series] 100 120 80
|
|
[Model] LVDS_model
Model_type I/O
Polarity Non-Inverting
Enable Active-Low
........
-----Original Message-----
From: sk [mailto:wsk78@yahoo.com]
Sent: 22. maj 2003 09:40
To: ibis-users@eda.org
Subject: [IBIS-Users] On-die DIFFERENTIAL terminated buffer modeling
Hi all,
Does anyone has experience modeling a LVDS input
buffer with on-die differential termination?
Can someone shed me some light here?
Best Regards
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