Subject: RE: [IBIS-Users] On-die DIFFERENTIAL terminated buffer modeling
From: Lynne Green (lgreen@cadence.com)
Date: Fri May 23 2003 - 08:06:30 PDT
Hi, Sk,
Using an external resistor puts it outside of the package parasitics (at
the package's external pins). This would produce different simulation
results compared to modeling the termination on-die.
You could try building an IBIS Package Model, with the on-die
termination connected at the die pads.
Regards,
Lynne
Dr. Lynne Green
Senior Member of Consulting Staff
Cadence Design Systems, Inc.
-----Original Message-----
From: Henrik G. Madsen [mailto:hgm@vitesse.com]
Sent: Thursday, May 22, 2003 11:38 PM
To: sk; ibis-users@eda.org
Subject: RE: [IBIS-Users] On-die DIFFERENTIAL terminated buffer modeling
Sk,
One solution could be to do the plain IBIS model for the LVDS input
without termination, and then adding the termination as a discrete
resistor in the simulation circuit.
The external termination resistor should of cause have the same
properties as the 'deleted' internal.
Regards
Henrik G Madsen
-----Original Message-----
From: sk [mailto:wsk78@yahoo.com]
Sent: 23. maj 2003 03:16
To: Henrik G. Madsen; ibis-users@eda.org
Subject: RE: [IBIS-Users] On-die DIFFERENTIAL terminated buffer modeling
Henrik,
Thanks for the reply. I just found out that the tool
that I'm using does not support the series keywords.
So does anyone has a workaround for this?
Much Appreciated,
sk
--- "Henrik G. Madsen" <hgm@vitesse.com> wrote:
> Hi
>
> If you have the SPICE model for the LVDS cell, you
> can remove the build-in termination and model the
> LVDS input as normal.
> Then afterwards, you can model the termination alone
> and add it to the IBIS file using the 'Series' model
> type.
> Remember to add the termination pin info through the
> [Series Pin Mapping] keyword
>
> I have tried to illustrate the final IBIS model
> below.
>
> You have to be aware that certain IBIS tool still do
> not support the below approach fully.
>
> Regards
> /Henrik G Madsen
>
> Example
> .......
> |
> [Pin] signal_name model_name
> R_pin L_pin C_pin
> |
> pin1 LVDS_p LVDS_model
> pin2 LVDS_n LVDS_model
> |
> [Diff pin] inv_pin vdiff tdelay_typ tdelay_min
> tdelay_max
> |
> pin1 pin2 NA NA NA NA
> |
> [Series Pin Mapping] pin_2 model_name
> function_table_group
> |
> pin1 pin2 term_model
> |
>
|***********************************************************************
|*
> [Model] term_model
> Model_type Series
> C_comp 0pF 0pF
> 0pF
> |
> [Temperature Range] 55.000 120.00
> 0.0000
> [Voltage Range] 2.500V 2.300V
> 2.700V
> |
> |variable R(typ) R(min) R(max)
> [R Series] 100 120 80
> |
> |
> [Model] LVDS_model
> Model_type I/O
> Polarity Non-Inverting
> Enable Active-Low
> ........
>
> -----Original Message-----
> From: sk [mailto:wsk78@yahoo.com]
> Sent: 22. maj 2003 09:40
> To: ibis-users@eda.org
> Subject: [IBIS-Users] On-die DIFFERENTIAL terminated
> buffer modeling
>
>
> Hi all,
>
> Does anyone has experience modeling a LVDS input
> buffer with on-die differential termination?
>
> Can someone shed me some light here?
>
> Best Regards
>
>
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