Subject: Re: [IBIS-Users] input termination
From: Timothy Coyle (timothy.coyle@sun.com)
Date: Fri Oct 03 2003 - 06:06:09 PDT
erik.van.der.ven@philips.com wrote:
>
> Hello IBIS experts,
>
> I have to model an LVDS input with internal termination.
>
> What is the best way to model this internal circuitry?
> What are the alternatives?
> And are the above implementations suitable for most IBIS simulators?
>
> In an input model Vinl and Vinh can be specified. This does not apply to my case since the absolute values are not of impotance, only the differential voltage matters. Is it enough to specify Vdiff in the [diff pin] keyword? Will Vinl and Vinh be ignored then? (since they also have default values normally).
>
> With kind regards,
> Erik.
>
> Ir. Erik van der Ven
> Room DB1032
> Business Line Networking Infrastructure
> Philips Semiconductors BV
> Gerstweg 2
> 6534 AE Nijmegen
> The Netherlands
> Phone: +31-24-3534334
Hi Erik,
First, you have to specify the Vinl and Vinh for your single-ended receiver inputs, or you will get parser warnings. Most IBIS simulators
will use the Vdiff value, as the spec states that this shall override the Vinh and Vinl parameters.
There's been previous discussion on this list (and SI List I believe) on how to include internal termination. One way is to use a series resistor, but
not all IBIS simulators support this. Others have suggested ways to extract the IBIS data with the resistor included. Search the Mentor Graphics
website or the IBSI website - Hazem Hegazy did a good presentation on LVDS modeling with internal terminations.
Regards,
Tim
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