Subject: RE: [IBIS-Users] Slew-Rate controlled output buffers
From: Muranyi, Arpad (arpad.muranyi@intel.com)
Date: Tue Feb 17 2004 - 09:20:48 PST
John,
You are forgetting all about the Vt curves. While it
is true that IV curves are the full DC characteristics
of the buffer, Vt curves provide the 0-100% scaling
factor vs. time information for it. I.e., Vt curves
are usually used to scale the IV curves as time goes
by to model how the buffer turns on/off with respect
to time. The shape of the Vt curve determines the
"slew rate".
Regarding the slew rate controlled buffers, based on your
description it sounds like you have some sort of a feedback
in mind which ensures that regardless of the load (within
a reasonable range) you get the same slew rate. You are
correct, such feedback is not possible with IBIS models
up to version 4.0. However, we just approved IBIS 4.1,
in which you can model practically anything you can think
of with the *-AMS language extensions.
However, I also have to say that when I hear about slew
rate controlled buffers, I rarely (or never) hear about
it as you described it. The "control" portion of the term
doesn't refer to a feedback loop, but a much simpler
mechanism to slow the edges down. The reason they do this
is because the latest technologies would allow the buffer
to switch a lot faster than desired for SI purposes, so
there must be some deliberate slowing in the design.
This can be very well modeled with regular IBIS models
using the appropriate Vt curves.
Are you sure that your slew rate controlled buffer is
as elaborate (using feedback) as you described it?
Arpad Muranyi
Intel Corporation
============================================================
-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On
Behalf Of John Phillippe
Sent: Tuesday, February 17, 2004 8:35 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] Slew-Rate controlled output buffers
I've been looking into the best way to model slew-rate controlled output
buffers in IBIS. It is my current understanding that IBIS doesn't
really support this. When I say slew-rate controlled output buffer, the
best way to describe it would be that for a given load range, say
10pF-100pF the output buffer will always have the same slew-rate.
Unlike say a simple cmos inverter where if you increase the output load,
the slew rate will slow down. The biggest issue in my mind is the I/V
curves. Since they are a DC sweep, you always get the highest drive on
the output buffers. Has anybody tackled this issue? Anyone have any
thoughts/solutions?
-- John Phillippe SPS, 32 Bit Embedded Controller Division, IC Creation Motorola - 512-895-1835 Austin, TX - john.phillippe@motorola.com|------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis <optional e-mail address, if different> | subscribe ibis-users <optional e-mail address, if different> | unsubscribe ibis <optional e-mail address, if different> | unsubscribe ibis-users <optional e-mail address, if different> | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993
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