IBIS-USERS - EIA IBIS Open Forum Users Activity: RE: [IBIS-Users

From: Mirmak, Michael <michael.mirmak@intel.com>
Date: Wed Jun 02 2004 - 09:02:43 PDT

Nirav,

Thanks for your interest in IBIS. Making an assumption that buffer
capacitance is "almost constant at all frequencies" may not be valid in
all, or even many, cases. Presentations and discussions at recent IBIS
summits have shown that serial differential interface buffers can show a
marked difference in capacitance values with both bias voltage and
frequency. Additionally, some of these buffers show a large
differential capacitance (an apparent capacitance across the output
terminals) in addition to the common mode capacitance between each
terminal and ground.

Presentations of interest are linked below:

http://www.eda.org/pub/ibis/summits/oct03/muranyi.pdf
http://www.ibis-information.org/summits/apr04/mirmak2.pdf

You may wish to perform a frequency sweep and a voltage bias sweep to
build a surface of your design's capacitive behaviors. While IBIS 4.0
does not allow direct use of such data, you can at least get an idea of
the device frequency response to aid you in selecting a c_comp value.
Certainly, IBIS 4.1 could incorporate this kind of surface information
through the VHDL-AMS and Verilog-AMS extensions.

- Michael Mirmak
Intel Corp.
Chair, EIA/IBIS Open Forum

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of Nirav Patel
Sent: Tuesday, June 01, 2004 9:34 PM
To: Robert Haller
Cc: ibis-users@eda.org
Subject: Re: [IBIS-Users] Re: High frequency performance of IBIS model

Bob,

Thanks for your inputs. So far we are able to build IBIS models
which correlated well till 1GHz (most complex ones are LVDS
terminated). Now, SerDes buffers, which suppose to run at 2.5GHZ,
need to model. I am sure there will be special circuits, still
we like to give a try.

At first, we like to match buffer level behavior of hspice and
IBIS, so we are not worried about package model as of now.

Generally, we extract output capacitance at 100MHz, for all our
buffers, assuming that C_comp is almost constant at all frequencies.
I like to understand why we have to study input versus output
capacitance when it comes to high frequency?

Thanks,
Nirav

Robert Haller wrote:
> Nirav,
>
> A accurate IBIS model can be constructed that correlates to SPICE and
> bench at 2.5 Ghz. Yes there can be limitations in models depending on

> the I/O cell circuit design, and the simulator. Some of the potential
> issues;
>
> - Was the model accurately constructed ?
> - Accuracy of package model
> - Does the I/O cell use special circuit tricks that IBIS may have
> difficulty modeling (or the model creator doesn't capture)
> - Crossover current in the I/O cell
> - Input capacitance versus output capacitance (C_comp) on I/O cell
>
> regards,
> Bob
>
>
> Nirav Patel wrote:
>
>> Hi All,
>>
>> I need your help to get more clarification on the following issues:
>>
>> 1. Simulators are capable of handling IBIS model which needs to run
at
>> 2.5 GHz.
>> 2. Is there any limitation in IBIS specification for characterizing
>> any buffer
>> which is operating at 2.5GHz.
>>
>> Thanks
>> Nirav
>>
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RE: [IBIS-Users] Re: High frequency performance of IBIS model