RE: [IBIS-Users] How to do Chip level IBIS Modelling.

Answers are inserted.
- Lynne

"IBIS training when you need it, where you need it."

Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@mindspring.com

________________________________________
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of palaniappan.sivakumar@wipro.com
Sent: Wednesday, October 06, 2004 5:34 AM
To: ibis-users@eda.org
Cc: owner-ibis-users@eda.org
Subject: [IBIS-Users] How to do Chip level IBIS Modelling.

Hi Experts,
 
It would be of great help if any one could let me know how the Chip level
IBIS modelling is done. 
We would like to understand the chip level IBIS models and its generation in
detail.
 
As we know chip level IBIS modelling includes number of Pins and its pkg
parameters, how do we include pad pins and pkg parasitics?
LG - Pins are associated with the I/O buffer model (buffer type) using the
IBIS keyword [Pin]. One can associate package parasitics at the [Component]
or for each individual [Pin], or for the component's package.
 
Can I specify more than one pkg models available in more than one ..pkg file
in to an IBIS model? if so how?
LG - Yes. You can use [Package Model] to provide a detailed package model.
One can also provide alternate package models.
 
Can any one know where can I get some guidelines for Chip level IBIS model
creation.?
LG - Since this is your first complete IBIS file, please consider sending it
to the IBIS Model Review Committee for their comments.
 
Any guidance would be appreciated.
LG - An excellent place to start is Arpad Muranyi's training materials,
which are posted on the IBIS Training page.
 
Thanks in Advance.
 
Regards,
Sivakumar
 
 

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Received on Wed Oct 6 09:04:32 2004