RE: [IBIS-Users] V-t curves offset

To all who responded,

If you read the question carefully, he was wondering why
after the shifting of the Vt curves he was still getting
different delays when changing the edge rate of the input
stimulus. Bob Ross was the only one who answered this
question! The IBIS model will switch when the stimulus
on its input reaches the switching threshold. (This could
be different in different simulators). After changing the
slope, the stimulus will take a different amount of time
to reach this threshold, causing a different delay.

It is also true that the internal buffer delay is
meaningless with IBIS models, but if the IBIS data
was extracted from a SPICE with steep edge rates on
the input of the SPICE model then the amount of error
in this delay will be minimal and the IBIS model should
be able to create overlapping waveforms without this
kind of a shift.

Arpad Muranyi
Intel Corporation
==========================================================

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of RODRIGUEZ_LECONA_RAMIRO
Sent: Tuesday, October 12, 2004 5:36 PM
To: ibis-info@eda.org; ibis-users@eda.org
Subject: [IBIS-Users] V-t curves offset

Hi all,

     I'm working with IBIS models validation and I have a problem
correlating the IBIS model with transistor level buffer in HSPICE. I
simulate both buffers with the same conditions (same load, temperature,
voltage supply) and the rising/falling edges of the outputs are equal but
there is a delay between IBIS model output waveform and transistor level
buffer output waveform. I shift the V-t Tables in the IBIS model to
compensate the delay and the output waveforms are matched but this occurs
when the input signal has rising/falling times equal to the rising/falling
times used to extract the IBIS model, if I use a input signal with
rising/falling times lower than the rising/falling times used to extract the
V-t curves then the buffer implemented with the IBIS model has again a
delay.
   What happens?
   How can I understand this? How can I avoid this delay?
   Or this phenomenom is normal because the important thing is the edge
waveform (buffer switching behavior) and the delay obtained is not relevant?
   Or the V-t curves obtained with specyfic rise/fall times are only valid
to simulate buffers with input signals with the same rise/fall times ?

   Thanks.

   Regards.

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Received on Wed Oct 13 08:47:14 2004