[IBIS-Users] BIRD 95 Comments.

Hello All

I sure think that BIRD 95 is very important and will enhance IBIS
modeling a step foreword.
Power Integrity Analysis is very important part when evaluation the
performance of an interface.

My notes to SSO/ SSN analysis using IBIS based on my experience.

I have tried to connect an IBIS model with inductive supply and compare
it to its SPICE source pad with the same conditions.
(when comparing the IBIS to the SPICE using ideal supply the results are
the same).
The results I got were:
1. The power drop in the IBIS power terminal was bigger then the spice.
2. The signal degradation (rise time) was bigger in the spice (the spice
has a significant degradation of the rise time while the IBIS looked
almost the same as ideal supply case).

This results mismatch since I would expect that in the system with the
bigger drop in the power rail the bigger degradation of the signal would be.

I have to mention that I have tried it in one simulation tool and I am
relaying on the tool implementation of IBIS (I didn't try to implement
myself the IBIS using primitive parts).

And now for the question: Assuming that the currents I_bypass, I_pre,
I_term in BIRD 95 diagram are totally zero. This is the case for the
current IBIS modeling that we have without BIRD 95. I will expect lower
current consumption then the real SPICE and as a results lower power
drop in the IBIS.
Also I would expect degradation of the rise time like the spice. This is
contrary to what I have seen and describe above.

Because of that I have tried to ask in the teleconference (7/jan) if
there's an algorithm that IBIS can mimic Spice when the power supply drop.
I think that BIRD 95 can led us to the ability to get more accurate
current consumption of the IBIS Buffer and then we get the response of
the power system to this currents and get the power supply voltage drop.
In this point if IBIS cant translate this voltage drop to a correct
behavior in the IO pin then all the effort is useless.

I would like also to know if some one has tried to compare IBIS to SPICE
on non ideal power supply and got good correlation.
I can implement the IBIS myself in the simulation tool, If theoretically
IBIS can give the right results in the IO pin due to the voltage drop
(Can someone back this up
and provide some feedback on that).

And back to BIRD 95:

The current is measured with the resistance and inductance of the power
supply rail of the pad. While the rising and falling v(t) table are
measured with ideal supply.
Isn't it better to measure the current on an ideal supply so the current
is correlated to the voltage response that was capture in the rising or
falling wave form.
Please elaborate why the current is measured with the inductance and
resistance.

-- 
Regards
Itzik Peleg 
Board Technology Group
Marvell Semiconductor Israel Ltd
6 Ha'mada St. Industrial Area
P.O.Box 692 Yokneam  20692  ISRAEL
Email - itzik.peleg@il.marvell.com
Tel   - +972 4  9091192  
Cell  - +972 54 4452482
Fax   - +972 4  9091501
WWW Page: http://www.marvell.com
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