RE: [IBIS-Users] RE: [IBIS] To capture the delay variation with change in IO voltage

Venu,
 
I am sorry, but I am not sure what to say now,
because I don't understand what you are referring
to as "pre-drivers section delay".  Please
clarify.
 
Thanks,
 
Arpad
==================================================

________________________________

From: Ummalaneni, Venu Babu (Venu) [mailto:venubabu@agere.com] 
Sent: Thursday, February 09, 2006 9:32 PM
To: Muranyi, Arpad; ibis-users@eda.org; ibis@eda.org
Cc: Kotikalapudi, Shiva Kumar (Shiva)
Subject: RE: [IBIS-Users] RE: [IBIS] To capture the delay variation with change in IO voltage 



Arpad,

 

I have tried with the 'scal' parameters that you have mentioned. Still correlation has not improved. I hope the pre-driver section delay, that influenced by IO voltage, may not scale by this option. I think "non-scalable pre-driver section delay" is one of the main causes for the mismatch in delay of IBIS vs spice models during IO voltage noise simulation. Please let me know your views.

 

Thanks,

Venu

 

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Muranyi, Arpad
Sent: Wednesday, February 08, 2006 11:10 PM
To: ibis-users@eda.org; ibis@eda.org
Subject: RE: [IBIS-Users] RE: [IBIS] To capture the delay variation with change in IO voltage 

 

Venu,

 

I just remembered something that I forgot to mention

in my previous reply.

 

This is not an IBIS parameter, but HSPICE does have something

in the B-element which tries to imitate the gate modulation

effect.  Look at the last two items on this list:

 

 

B_IO nd_pu nd_pd nd_out nd_in nd_en V_out_of_in [nd_pc nd_gc]
+ file='file_name' model='model_name'
+ [typ={typ|min|max|fast|slow}] [power={on|off}]
+ [buffer={3|input_output}]
+ [xv_pu=state_pu] [xv_pd=state_pd]
+ [interpol={1|2}]
+ [ramp_fwf={2|1|0}] [ramp_rwf={2|1|0}]
+ [fwf_tune=fwf_tune_value] [rwf_tune=rwf_tune_value]
+ [nowarn]
+ [c_com_pu=c_com_pu_value]
+ [c_com_pd=c_com_pd_value]
+ [c_com_pc=c_com_pc_value]
+ [c_com_gc=c_com_gc_value]
+ [pu_scal=pu_scal_value]
+ [pd_scal=pd_scal_value]
+ [pc_scal=pc_scal_value]
+ [gc_scal=gc_scal_value]
+ [rwf_scal=rwf_scal_value]
+ [fwf_scal=fwf_scal_value]
+ [spu_scal=spu_scal_value]
+ [spd_scal=spd_scal_value]

 

 

They are scaling coefficients which scale the IV curves based

on the change in the supply voltage.  They are not documented

too well in the HSPICE manuals, but as far as I remember they

will do the following:

 

If you have a value of 1, the IV curve will be scaled by the

same percentage as the supply deviates from the value given

by the IBIS model.  For example, a 5V buffer getting 4.5 volts

means a 10% change down, so the IV curve will be reduced by 10%.

If you give 0.5 for these parameters, the same 10% change in the

supply will result in 5% change in the IV curve.  A zero will

result in no change in the IV curves, a 2 will result a 20%

change, and so on...  As far as I remember, negative values will

also work reversing the relationship (lower supplies will increase

the IV curves).

 

I hope this helps.

 

Arpad

===============================================================


 

________________________________

From: Ummalaneni, Venu Babu (Venu) [mailto:venubabu@agere.com] 
Sent: Wednesday, February 08, 2006 1:51 AM
To: Muranyi, Arpad
Cc: Kotikalapudi, Shiva Kumar (Shiva); Patel, Nirav (Nirav)
Subject: RE: [IBIS-Users] RE: [IBIS] To capture the delay variation with change in IO voltage 

Arpad,

 

It is good to know that IBIS forum is actively working on these features.

Thank you very much for the very detailed response and pointers.

 

Best Regards,

Venu

 

 

-----Original Message-----
From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Muranyi, Arpad
Sent: Tuesday, February 07, 2006 11:16 PM
To: ibis-users@eda.org; ibis@eda.org
Subject: RE: [IBIS-Users] RE: [IBIS] To capture the delay variation with change in IO voltage 

 

Venu,

 

The IBIS model will only partially for the Vcc variations.

Here is how:

 

If you lower the supply voltage, the origin of the pullup

IV curve will go down to that lower voltage.  So the pullup

will pull up to a lower voltage.

 

However, in real transistor circuits, this lower supply

voltage would also reduce the IV curve size, because the

Vgs voltage is smaller than at the normal supply voltage.

This effect is usually called the "gate modulation effect"

and is not reproduced by IBIS simulators to my knowledge.

We are working on BIRD98 to describe this effect for IBIS

models.

 

http://www.vhdl.org/pub/ibis/birds/bird98.txt

 

There may be two reasons for being interested in supply

voltage variations.

 

1)  Static DC characteristics of the buffer, i.e. how

much will its strength change if we change the supply

voltage.  If you need this, you can generate several IV

curves at different supply voltages and make a [Model]

for each set.  You can then use the [Model Selector]

keyword to allow the tool to select the one you want

to simulate with.

 

2)  Dynamic noise simulations, i.e. you want to find

out how the buffer will "degrade" its switching performance

when there is noise in the supply voltage during its

switching.  This is a more difficult task, and IBIS is

not doing too well on it.  We have BIRD95 and BIRD98 as

Lynne mentioned it already to solve this deficiency in

the IBIS world.  However, as usual, if you write your

own models in the *-AMS languages, you can describe these

behaviors to your heart's content without having to wait

for BIRD95 and BIRD98.

 

I hope this will shed some light on your questions.

 

Arpad

=========================================================


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